Re: [U-Boot] [PATCH] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

On 02/01/2017 05:49 AM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination and move existing register

[U-Boot] [PATCH] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination and move existing register space definaton of CCI-400 bus from from immap_lsch2