Re: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-26 Thread Stefano Babic
On 20/05/2015 04:28, Peng Fan wrote: > We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee > that socs' cache line size is 32 bytes. > If on chips whose cache line size is 64 bytes, error occurs: > " > NAND: ERROR: v7_dcache_inval_range - start address is not aligned - > 0x

Re: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-25 Thread Peng Fan
Hi Stefano, On Thu, May 21, 2015 at 09:16:32AM +0800, Peng Fan wrote: >Hi Marek, > >On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote: >>On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote: >>> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee >>> that socs

Re: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-21 Thread Peng Fan
Hi Marek, On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote: >On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote: >> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee >> that socs' cache line size is 32 bytes. >> If on chips whose cache line size is 64 byt

Re: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-21 Thread Marek Vasut
On Thursday, May 21, 2015 at 03:16:32 AM, Peng Fan wrote: > Hi Marek, Hi! > On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote: > >On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote: > >> We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not > >> guarantee that socs' ca

Re: [U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-20 Thread Marek Vasut
On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote: > We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee > that socs' cache line size is 32 bytes. > If on chips whose cache line size is 64 bytes, error occurs: Which chips are those? > NAND: ERROR: v7_dcache_inval_r

[U-Boot] [PATCH] imx: dma: correct MXS_DMA_ALIGNMENT

2015-05-19 Thread Peng Fan
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop addre