From: Tang Yuantian <yuantian.t...@freescale.com>
Freescale ARM-based Layerscape SoCs contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds some basic SATA APIs which would be called by
specific board.
Signed-off-by: Tang Yuantian <yuantian.t...@freescale.com>
---
board/freescale/common/Makefile | 6 +++++
board/freescale/common/ls_sata.c | 52 ++++++++++++++++++++++++++++++++++++++++
board/freescale/common/ls_sata.h | 39 ++++++++++++++++++++++++++++++
3 files changed, 97 insertions(+)
create mode 100644 board/freescale/common/ls_sata.c
create mode 100644 board/freescale/common/ls_sata.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 87d0578..8508005 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -43,6 +43,12 @@ else
obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
+ifdef CONFIG_ARM
+ifdef CONFIG_SATA1
+obj-y += ls_sata.o
+endif
+endif
+
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
diff --git a/board/freescale/common/ls_sata.c b/board/freescale/common/ls_sata.c
new file mode 100644
index 0000000..2aab939
--- /dev/null
+++ b/board/freescale/common/ls_sata.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <ahci.h>
+#include <scsi.h>
+
+#include "ls_sata.h"
+
+void ls_sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+ unsigned int __iomem *dcfg_ecc = (void *)0x20220520;
+ out_le32(dcfg_ecc, 0x00020000);
+#endif
+
+#ifdef CONFIG_SATA2
+ ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA2;
+ out_le32(&ccsr_ahci->ppcfg, 0xa003fffe);
+#endif
+
+#ifdef CONFIG_SATA1
+ ccsr_ahci = (void __iomem *)CONFIG_SYS_SATA1;
+ out_le32(&ccsr_ahci->ppcfg, 0xa003fffe);
+#ifdef CONFIG_LS102XA
+ out_le32(&ccsr_ahci->pp2c, 0x28183411);
+ out_le32(&ccsr_ahci->pp3c, 0x0e081004);
+ out_le32(&ccsr_ahci->pp4c, 0x00480811);
+ out_le32(&ccsr_ahci->pp5c, 0x192c96a4);
+ out_le32(&ccsr_ahci->ptc, 0x08000025);
+#endif
+#endif
+}
+
+int ls_sata_start(void)
+{
+ int rc;
+
+ rc = ahci_init((void *)CONFIG_SYS_SATA1);
+ if (rc)
+ return rc;
+
+ scsi_scan(0);
+
+ return 0;
+}
diff --git a/board/freescale/common/ls_sata.h b/board/freescale/common/ls_sata.h
new file mode 100644
index 0000000..a69854c
--- /dev/null
+++ b/board/freescale/common/ls_sata.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS_SATA_H
+#define __LS_SATA_H
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 paxic; /* port AXI config */
+ u32 axicc; /* AXI cache control */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc; /* port Trans Config */
+ u32 pts; /* port Trans Status */
+ u32 plc; /* port link config */
+ u32 plc1; /* port link config1 */
+ u32 plc2; /* port link config2 */
+ u32 pls; /* port link status */
+ u32 pls1; /* port link status1 */
+ u32 pcmdc; /* port CMD config */
+ u32 ppcs; /* port phy control status */
+ u32 pberr; /* port 0/1 BIST error */
+ u32 cmds; /* port 0/1 CMD status error */
+};
+
+void ls_sata_init(void);
+
+int ls_sata_start(void);
+
+#endif
--
2.1.0.27.g96db324
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