When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun <york...@freescale.com>
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 +-
2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index c3e1d76..936c195 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -236,9 +236,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ unsigned int data_rate = fsl_ddr_get_mem_data_rate();
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
+ if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
+ twrt_mclk = 1;
if (popts->dynamic_power == 0) { /* powerdown is not used */
act_pd_exit_mclk = 1;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 35b60a0..c7c12c1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -80,5 +80,5 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
extern unsigned int mclk_to_picos(unsigned int mclk);
extern unsigned int get_memory_clk_period_ps(void);
extern unsigned int picos_to_mclk(unsigned int picos);
-
+extern unsigned int fsl_ddr_get_mem_data_rate(void);
#endif
--
1.7.0.4
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