On Tue, 2009-09-15 at 23:11 -0500, Kumar Gala wrote:
> On Sep 15, 2009, at 10:32 PM, Peter Tyser wrote:
>
> > On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
> >> For some reason the CLKDIV field varies between SoC in how it
> >> interprets
> >> the bit values.
> >>
> >> All 83xx and early
Peter Tyser a écrit :
> On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
>
>> For some reason the CLKDIV field varies between SoC in how it interprets
>> the bit values.
>>
>>
[snip]
>>
>> Ensure that the MPC86xx and MPC85xx still get the same behavior and make
>> the the defines refl
On Sep 15, 2009, at 10:32 PM, Peter Tyser wrote:
> On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
>> For some reason the CLKDIV field varies between SoC in how it
>> interprets
>> the bit values.
>>
>> All 83xx and early (e500v1) PQ3 devices support:
>> clk/2: CLKDIV = 2
>> clk/4: CLKDIV
On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
> For some reason the CLKDIV field varies between SoC in how it interprets
> the bit values.
>
> All 83xx and early (e500v1) PQ3 devices support:
> clk/2: CLKDIV = 2
> clk/4: CLKDIV = 4
> clk/8: CLKDIV = 8
>
> Newer PQ3 (e500v2) and MPC86xx
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.
All 83xx and early (e500v1) PQ3 devices support:
clk/2: CLKDIV = 2
clk/4: CLKDIV = 4
clk/8: CLKDIV = 8
Newer PQ3 (e500v2) and MPC86xx support:
clk/4: CLKDIV = 2
clk/8: CLKDIV = 4
clk/16: CLKDIV = 8
Ens
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