The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transctions in SPL.
To work around this issue, we disable DMA-based access modes in the
SPL stage. Note that this affects full OF_CONTROL (i.e. OF_PLATDATA
not being defined) only and aligns the behaviour with what happens
when OF_PLATDATA is defined, as fifo_mode gets overwritten to 0 in
that case.
With this fix in place, we can reenable 'fifo-mode' in the DTS for
the RK3399-Q7 (Puma).
Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
arch/arm/dts/rk3399-puma.dts | 1 -
drivers/mmc/rockchip_dw_mmc.c | 11 +++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
index 917df1e..71eb72d 100644
--- a/arch/arm/dts/rk3399-puma.dts
+++ b/arch/arm/dts/rk3399-puma.dts
@@ -91,7 +91,6 @@
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
- fifo-mode; /* until we fix DMA in SPL */
status = "okay";
};
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index c36eda0..6bf4823 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -76,6 +76,17 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice
*dev)
return -EINVAL;
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
+
+#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
+ /*
+ * For a RK3399 SPL build, force fifo_mode to off as the MMC
+ * transaction will otherwise hang. This issue reproduces
+ * only SPL (i.e. BL2 in ATF terminology), but doesn't occur
+ * with the full U-Boot stage.
+ */
+ priv->fifo_mode = 0;
+#endif
+
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
--
1.9.1
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