Re: [U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
Hi, On 18-12-14 19:59, Ian Campbell wrote: On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: @@ -128,7 +128,8 @@ #define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUNXI_P2WI_BASE0x01f03400 +#define SUNXI_P2WI_BASE0x01f03400 /* on sun6i */ +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ Maybe we just use SUN6I_ SUN8I_ prefixes? The base address will be different on sun9i. Did you miss this suggestions from Chen-Yu? Seems like a good one. Yes I missed that (must have read over it). That will work for P2Wi, but not for RSB, as RSB is used on the A80 too AFAIK, but I guess having P2WI as SUN6I and RSB as SUNXI makes it clear what is used where, so I'll update the patch with that change. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: Hi, On 17-12-14 03:22, Chen-Yu Tsai wrote: Hi, On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede hdego...@redhat.com wrote: sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Note: Not yet ready for upstream, code needs some significant cleanups. Confusing note. Ugh, I forgot to remove that note after doing the cleanups, I'll remove it from the version of the patch my personal tree :) I'll stop ignoring this patch then ;-) Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: @@ -128,7 +128,8 @@ #define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUNXI_P2WI_BASE0x01f03400 +#define SUNXI_P2WI_BASE0x01f03400 /* on sun6i */ +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ Maybe we just use SUN6I_ SUN8I_ prefixes? The base address will be different on sun9i. Did you miss this suggestions from Chen-Yu? Seems like a good one. I don't have any other comments. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
Hi,
On 17-12-14 03:22, Chen-Yu Tsai wrote:
Hi,
On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede hdego...@redhat.com wrote:
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Note: Not yet ready for upstream, code needs some significant cleanups.
Confusing note.
Ugh, I forgot to remove that note after doing the cleanups, I'll remove it
from the version of the patch my personal tree :)
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/rsb.c | 158 +
arch/arm/include/asm/arch-sunxi/cpu.h | 3 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/prcm.h | 3 +-
arch/arm/include/asm/arch-sunxi/rsb.h | 55
6 files changed, 220 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c
create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 1337b60..3e8975a 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,6 +15,7 @@ obj-y += pinmux.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
new file mode 100644
index 000..b72bb9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * lixiang lixi...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/prcm.h
+#include asm/arch/rsb.h
+
+static void rsb_cfg_io(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+}
+
+static void rsb_set_clk(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 2400 / 300 / 2 - 1;
+ cd_odly = div 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly 8) | div, rsb-ccr);
+}
+
+void rsb_init(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ rsb_cfg_io();
+
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ writel(RSB_CTRL_SOFT_RST, rsb-ctrl);
Do we need a small delay here for the device to finish reset?
Maybe, this (no delay) is what the allwinner code was doing, and it
seems to work fine ...
+ rsb_set_clk();
+}
+
+static int rsb_await_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(rsb-stat);
+ if (stat RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, rsb-stat); /* Clear status bits */
+
+ return ret;
+}
+
+int rsb_set_device_mode(u32 device_mode_data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, rsb-dmcr);
+
+ while (readl(rsb-dmcr) RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() tmo)
+ return -ETIME;
+ }
+
+ return
[U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Note: Not yet ready for upstream, code needs some significant cleanups.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/rsb.c | 158 +
arch/arm/include/asm/arch-sunxi/cpu.h | 3 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/prcm.h | 3 +-
arch/arm/include/asm/arch-sunxi/rsb.h | 55
6 files changed, 220 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c
create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 1337b60..3e8975a 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,6 +15,7 @@ obj-y += pinmux.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
new file mode 100644
index 000..b72bb9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * lixiang lixi...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/prcm.h
+#include asm/arch/rsb.h
+
+static void rsb_cfg_io(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+}
+
+static void rsb_set_clk(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 2400 / 300 / 2 - 1;
+ cd_odly = div 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly 8) | div, rsb-ccr);
+}
+
+void rsb_init(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ rsb_cfg_io();
+
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ writel(RSB_CTRL_SOFT_RST, rsb-ctrl);
+ rsb_set_clk();
+}
+
+static int rsb_await_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(rsb-stat);
+ if (stat RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, rsb-stat); /* Clear status bits */
+
+ return ret;
+}
+
+int rsb_set_device_mode(u32 device_mode_data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, rsb-dmcr);
+
+ while (readl(rsb-dmcr) RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() tmo)
+ return -ETIME;
+ }
+
+ return rsb_await_trans();
+}
+
+static int rsb_do_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ setbits_le32(rsb-ctrl, RSB_CTRL_START_TRANS);
+ return rsb_await_trans();
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+
Re: [U-Boot] [PATCH 02/14] sunxi: Add support for the rsb (Reduced Serial Bus)
Hi,
On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede hdego...@redhat.com wrote:
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Note: Not yet ready for upstream, code needs some significant cleanups.
Confusing note.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/rsb.c | 158
+
arch/arm/include/asm/arch-sunxi/cpu.h | 3 +-
arch/arm/include/asm/arch-sunxi/gpio.h | 2 +
arch/arm/include/asm/arch-sunxi/prcm.h | 3 +-
arch/arm/include/asm/arch-sunxi/rsb.h | 55
6 files changed, 220 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c
create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 1337b60..3e8975a 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,6 +15,7 @@ obj-y += pinmux.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
new file mode 100644
index 000..b72bb9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * lixiang lixi...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/prcm.h
+#include asm/arch/rsb.h
+
+static void rsb_cfg_io(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+}
+
+static void rsb_set_clk(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 2400 / 300 / 2 - 1;
+ cd_odly = div 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly 8) | div, rsb-ccr);
+}
+
+void rsb_init(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ rsb_cfg_io();
+
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ writel(RSB_CTRL_SOFT_RST, rsb-ctrl);
Do we need a small delay here for the device to finish reset?
+ rsb_set_clk();
+}
+
+static int rsb_await_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(rsb-stat);
+ if (stat RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, rsb-stat); /* Clear status bits */
+
+ return ret;
+}
+
+int rsb_set_device_mode(u32 device_mode_data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, rsb-dmcr);
+
+ while (readl(rsb-dmcr) RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() tmo)
+ return -ETIME;
+ }
+
+ return rsb_await_trans();
+}
+
+static int rsb_do_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg
