On Mon, 2015-01-19 at 20:04 +0100, Hans de Goede wrote:
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to 1 before the caches and MMU are
Hello Hans,
On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede hdego...@redhat.com
wrote:
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to
Hi,
On 20-01-15 11:22, Albert ARIBAUD wrote:
Hello Hans,
On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede hdego...@redhat.com
wrote:
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference
Hello Hans,
On Tue, 20 Jan 2015 15:32:34 +0100, Hans de Goede hdego...@redhat.com
wrote:
Hi,
On 20-01-15 11:22, Albert ARIBAUD wrote:
Hello Hans,
I'm leaning toward grouping all CP15 inits (including cache(s)
and TLB disabling and maybe VBAR setting) in a single CP15 call to
a
Hello Hans,
On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede hdego...@redhat.com
wrote:
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to
Hi,
On 17-01-15 23:51, Ian Campbell wrote:
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to 1 before the caches and MMU are enabled,
or any cache and TLB maintenance operations are
On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to 1 before the caches and MMU are enabled,
or any cache and TLB maintenance operations are performed.
Given that this is a feature of the
According to the Cortex-A7 MPCore Technical Reference Manual:
You must ensure this bit is set to 1 before the caches and MMU are enabled,
or any cache and TLB maintenance operations are performed.
Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
we should thus
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