From: Scott Jiang scott.jiang.li...@gmail.com
Spi driver for bf60x is different from old one, so implement a new
driver for it.
Signed-off-by: Scott Jiang scott.jiang.li...@gmail.com
Signed-off-by: Sonic Zhang sonic.zh...@analog.com
Signed-off-by: Bob Liu lliu...@gmail.com
---
.../blackfin/include/asm/mach-common/bits/spi6xx.h | 240 +++
drivers/spi/Makefile |1 +
drivers/spi/bfin_spi6xx.c | 308
include/configs/bf609-ezkit.h |9 +
4 files changed, 558 insertions(+)
create mode 100644 arch/blackfin/include/asm/mach-common/bits/spi6xx.h
create mode 100644 drivers/spi/bfin_spi6xx.c
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
new file mode 100644
index 000..535a24a
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
@@ -0,0 +1,240 @@
+/*
+ * Analog Devices SPI3 controller driver
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPI_CHANNEL_H_
+#define _SPI_CHANNEL_H_
+
+#include linux/types.h
+
+/* SPI_CONTROL */
+#define SPI_CTL_EN 0x0001/* Enable */
+#define SPI_CTL_MSTR0x0002/* Master/Slave */
+#define SPI_CTL_PSSE0x0004/* controls modf error in
master mode */
+#define SPI_CTL_ODM 0x0008/* Open Drain Mode */
+#define SPI_CTL_CPHA0x0010/* Clock Phase */
+#define SPI_CTL_CPOL0x0020/* Clock Polarity */
+#define SPI_CTL_ASSEL 0x0040/* Slave Select Pin Control
*/
+#define SPI_CTL_SELST 0x0080/* Slave Select Polarity
in-between transfers */
+#define SPI_CTL_EMISO 0x0100/* Enable MISO */
+#define SPI_CTL_SIZE0x0600/* Word Transfer Size */
+#define SPI_CTL_SIZE08 0x/* SIZE: 8 bits */
+#define SPI_CTL_SIZE16 0x0200/* SIZE: 16 bits */
+#define SPI_CTL_SIZE32 0x0400/* SIZE: 32 bits */
+#define SPI_CTL_LSBF0x1000/* LSB First */
+#define SPI_CTL_FCEN0x2000/* Flow-Control Enable */
+#define SPI_CTL_FCCH0x4000/* Flow-Control Channel
Selection */
+#define SPI_CTL_FCPL0x8000/* Flow-Control Polarity */
+#define SPI_CTL_FCWM0x0003/* Flow-Control Water-Mark */
+#define SPI_CTL_FIFO0 0x/* FCWM: TFIFO empty or
RFIFO Full */
+#define SPI_CTL_FIFO1 0x0001/* FCWM: TFIFO 75% or more
empty or RFIFO 75% or more full */
+#define SPI_CTL_FIFO2 0x0002/* FCWM: TFIFO 50% or more
empty or RFIFO 50% or more full */
+#define SPI_CTL_FMODE 0x0004/* Fast-mode Enable */
+#define SPI_CTL_MIOM0x0030/* Multiple I/O Mode */
+#define SPI_CTL_MIO_DIS 0x/* MIOM: Disable */
+#define SPI_CTL_MIO_DUAL0x0010/* MIOM: Enable DIOM (Dual
I/O Mode) */
+#define SPI_CTL_MIO_QUAD0x0020/* MIOM: Enable QUAD (Quad
SPI Mode) */
+#define SPI_CTL_SOSI0x0040/* Start on MOSI */
+/* SPI_RX_CONTROL */
+#define SPI_RXCTL_REN 0x0001/* Receive Channel Enable */
+#define SPI_RXCTL_RTI 0x0004/* Receive Transfer Initiate
*/
+#define SPI_RXCTL_RWCEN 0x0008/* Receive Word Counter
Enable */
+#define SPI_RXCTL_RDR 0x0070/* Receive Data Request */
+#define SPI_RXCTL_RDR_DIS 0x/* RDR: Disabled */
+#define SPI_RXCTL_RDR_NE0x0010/* RDR: RFIFO not empty */
+#define SPI_RXCTL_RDR_250x0020/* RDR: RFIFO 25% full */
+#define SPI_RXCTL_RDR_500x0030/* RDR: RFIFO 50% full */
+#define SPI_RXCTL_RDR_750x0040/* RDR: RFIFO 75% full */
+#define SPI_RXCTL_RDR_FULL 0x0050/* RDR: RFIFO full */
+#define SPI_RXCTL_RDO 0x0100/* Receive Data Over-Run */
+#define SPI_RXCTL_RRWM 0x3000/* FIFO Regular Water-Mark */
+#define SPI_RXCTL_RWM_0 0x/*
