On 18/08/2019 15:42, Beniamino Galvani wrote:
> This adds support for the USB PHY found on Amlogic GXBB SoCs.
>
> Signed-off-by: Beniamino Galvani
> ---
> drivers/phy/Kconfig | 8 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/meson-gxbb-usb2.c | 235 ++
> 3 files changed, 244 insertions(+)
> create mode 100644 drivers/phy/meson-gxbb-usb2.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 3942f035eb..2190f6f970 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -154,6 +154,14 @@ config PHY_STM32_USBPHYC
> between an HS USB OTG controller and an HS USB Host controller,
> selected by an USB switch.
>
> +config MESON_GXBB_USB_PHY
> + bool "Amlogic Meson GXBB USB PHY"
> + depends on PHY && ARCH_MESON && MESON_GXBB
> + imply REGMAP
> + help
> + This is the generic phy driver for the Amlogic Meson GXBB
> + USB2 PHY.
> +
> config MESON_GXL_USB_PHY
> bool "Amlogic Meson GXL USB PHYs"
> depends on PHY && ARCH_MESON && (MESON_GXL || MESON_GXM)
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 3157f1b7ee..dde3b0ecef 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
> obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
> obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
> obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
> +obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
> obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
> obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
> obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
> diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c
> new file mode 100644
> index 00..88c2ec69b2
> --- /dev/null
> +++ b/drivers/phy/meson-gxbb-usb2.c
> @@ -0,0 +1,235 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Meson8, Meson8b and GXBB USB2 PHY driver
> + *
> + * Copyright (C) 2016 Martin Blumenstingl
>
> + * Copyright (C) 2018 BayLibre, SAS
> + *
> + * Author: Beniamino Galvani
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define REG_CONFIG 0x00
> + #define REG_CONFIG_CLK_EN BIT(0)
> + #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
> + #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
> + #define REG_CONFIG_CLK_32k_ALTSEL BIT(15)
> + #define REG_CONFIG_TEST_TRIGBIT(31)
> +
> +#define REG_CTRL 0x04
> + #define REG_CTRL_SOFT_PRST BIT(0)
> + #define REG_CTRL_SOFT_HRESETBIT(1)
> + #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
> + #define REG_CTRL_CLK_DET_RSTBIT(4)
> + #define REG_CTRL_INTR_SEL BIT(5)
> + #define REG_CTRL_CLK_DETECTED BIT(8)
> + #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9)
> + #define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
> + #define REG_CTRL_POWER_ON_RESET BIT(15)
> + #define REG_CTRL_SLEEPM BIT(16)
> + #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17)
> + #define REG_CTRL_TX_BITSTUFF_ENNBIT(18)
> + #define REG_CTRL_COMMON_ON BIT(19)
> + #define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)
> + #define REG_CTRL_REF_CLK_SEL_SHIFT 20
> + #define REG_CTRL_FSEL_MASK GENMASK(24, 22)
> + #define REG_CTRL_FSEL_SHIFT 22
> + #define REG_CTRL_PORT_RESET BIT(25)
> + #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
> +
> +/* bits [31:26], [24:21] and [15:3] seem to be read-only */
> +#define REG_ADP_BC 0x0c
> + #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
> + #define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
> + #define REG_ADP_BC_OTG_DISABLE BIT(2)
> + #define REG_ADP_BC_ID_PULLUPBIT(3)
> + #define REG_ADP_BC_DRV_VBUS BIT(4)
> + #define REG_ADP_BC_ADP_PRB_EN BIT(5)
> + #define REG_ADP_BC_ADP_DISCHARGEBIT(6)
> + #define REG_ADP_BC_ADP_CHARGE BIT(7)
> + #define REG_ADP_BC_SESS_END BIT(8)
> + #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9)
> + #define REG_ADP_BC_B_VALID BIT(10)
> + #define REG_ADP_BC_A_VALID BIT(11)
> + #define REG_ADP_BC_ID_DIG BIT(12)
> + #define REG_ADP_BC_VBUS_VALID BIT(13)
> + #define
