From: Rick Chen <r...@andestech.com>
Use same dts to boot U-Boot and RISC-V
Linux Kernel v4.16-rc2 in ax25-ae350 platform.
Signed-off-by: Rick Chen <r...@andestech.com>
Signed-off-by: Rick Chen <rickche...@gmail.com>
Cc: Greentime Hu <green...@gmail.com>
---
arch/riscv/dts/ae350.dts | 204 ++++++++++++++++++++++++++++-------------------
1 file changed, 122 insertions(+), 82 deletions(-)
diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts
index 4bfb876..f7d4190 100644
--- a/arch/riscv/dts/ae350.dts
+++ b/arch/riscv/dts/ae350.dts
@@ -1,97 +1,137 @@
/dts-v1/;
+
/ {
- compatible = "riscv32 ax25";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "andestech,ax25";
+ model = "andestech,ax25";
+
+ aliases {
+ uart0 = &serial0;
+ spi0 = &spi;
+ } ;
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000
debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ };
- aliases {
- uart0 = &serial0;
- ethernet0 = &mac0;
- spi0 = &spi;
- } ;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <10000000>;
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <60000000>;
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
- chosen {
- bootargs = "console=ttyS0,38400n8
earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- tick-timer = &timer0;
- };
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x40000000>;
+ };
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>;
- };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "andestech,riscv-ae350-soc";
+ ranges;
+ };
- spiclk: virt_100mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
+ plmt0@e6000000 {
+ compatible = "riscv,plmt0";
+ interrupts-extended = <&CPU0_intc 7>;
+ reg = <0x0 0xe6000000 0x0 0x100000>;
+ };
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "andestech,n13";
- reg = <0>;
- /* FIXME: to fill correct frqeuency */
- clock-frequency = <60000000>;
- };
- };
+ plic0: interrupt-controller@e4000000 {
+ compatible = "riscv,plic0";
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x0 0xe4000000 0x0 0x2000000>;
+ riscv,ndev=<31>;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+ };
- intc: interrupt-controller {
- compatible = "andestech,atnointc010";
- #interrupt-cells = <1>;
- interrupt-controller;
- };
+ plic1: interrupt-controller@e6400000 {
+ compatible = "riscv,plic1";
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x0 0xe6400000 0x0 0x400000>;
+ riscv,ndev=<1>;
+ interrupts-extended = <&CPU0_intc 3>;
+ };
- serial0: serial@f0300000 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0xf0300000 0x1000>;
- interrupts = <7 4>;
- clock-frequency = <19660800>;
- reg-shift = <2>;
- reg-offset = <32>;
- no-loopback-test = <1>;
- };
+ spiclk: virt_100mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
- timer0: timer@f0400000 {
- compatible = "andestech,atcpit100";
- reg = <0xf0400000 0x1000>;
- interrupts = <2 4>;
- clock-frequency = <40000000>;
- };
+ timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0x0 0xf0400000 0x0 0x1000>;
+ clock-frequency = <40000000>;
+ interrupts = <3 4>;
+ interrupt-parent = <&plic0>;
+ };
- mac0: mac@e0100000 {
- compatible = "andestech,atmac100";
- reg = <0xe0100000 0x1000>;
- interrupts = <25 4>;
- };
+ serial0: serial@f0300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x0 0xf0300000 0x0 0x1000>;
+ interrupts = <9 4>;
+ clock-frequency = <19660800>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ interrupt-parent = <&plic0>;
+ };
- mmc0: mmc@f0e00000 {
- compatible = "andestech,atsdc010";
- max-frequency = <100000000>;
- fifo-depth = <0x10>;
- reg = <0xf0e00000 0x1000>;
- interrupts = <17 4>;
- cap-sd-highspeed;
- };
+ mac0: mac@e0100000 {
+ compatible = "andestech,atmac100";
+ reg = <0x0 0xe0100000 0x0 0x1000>;
+ interrupts = <19 4>;
+ interrupt-parent = <&plic0>;
+ };
- spi: spi@f0b00000 {
- compatible = "andestech,atcspi200";
- reg = <0xf0b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- num-cs = <1>;
- clocks = <&spiclk>;
- interrupts = <3 4>;
- flash@0 {
- compatible = "spi-flash";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-cpol;
- spi-cpha;
- };
- };
+ mmc0: mmc@f0e00000 {
+ compatible = "andestech,atfsdc010";
+ max-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ fifo-depth = <0x10>;
+ reg = <0x0 0xf0e00000 0x0 0x1000>;
+ interrupts = <18 4>;
+ cap-sd-highspeed;
+ interrupt-parent = <&plic0>;
+ };
+ spi: spi@f0b00000 {
+ compatible = "andestech,atcspi200";
+ reg = <0x0 0xf0b00000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ clocks = <&spiclk>;
+ interrupts = <3 4>;
+ interrupt-parent = <&plic0>;
+ flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
};
--
2.7.4
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