The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver
Signed-off-by: Chunfeng Yun <chunfeng....@mediatek.com>
---
drivers/clk/mediatek/clk-mt7629.c | 42 +++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
index 30a919f224..858be85d15 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -539,6 +539,29 @@ static const struct mtk_gate sgmii_cgs[] = {
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
+};
+
static const struct mtk_clk_tree mt7629_clk_tree = {
.xtal_rate = 40 * MHZ,
.xtal2_rate = 20 * MHZ,
@@ -621,6 +644,11 @@ static int mt7629_sgmiisys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
}
+static int mt7629_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7629_apmixed_compat[] = {
{ .compatible = "mediatek,mt7629-apmixedsys" },
{ }
@@ -651,6 +679,11 @@ static const struct udevice_id mt7629_sgmiisys_compat[] = {
{ }
};
+static const struct udevice_id mt7629_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7629-ssusbsys" },
+ { }
+};
+
static const struct udevice_id mt7629_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7629-mcucfg" },
{ }
@@ -722,3 +755,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7629-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7629_ssusbsys_compat,
+ .probe = mt7629_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--
2.23.0
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