Re: [U-Boot] [PATCH 10/19] riscv: Add CSR numbers

Hi Lukas, On Thu, Nov 15, 2018 at 6:26 AM Auer, Lukas wrote: > > Hi Bin, > > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote: > > The standard RISC-V ISA sets aside a 12-bit encoding space for up > > to 4096 CSRs. This adds all known CSR numbers as defined in the > > RISC-V Privileged

Re: [U-Boot] [PATCH 10/19] riscv: Add CSR numbers

Hi Bin, On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote: > The standard RISC-V ISA sets aside a 12-bit encoding space for up > to 4096 CSRs. This adds all known CSR numbers as defined in the > RISC-V Privileged Architecture Version 1.10. > > Signed-off-by: Bin Meng > --- > >

[U-Boot] [PATCH 10/19] riscv: Add CSR numbers

The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng --- arch/riscv/include/asm/encoding.h | 219 ++ 1 file