Hi Rick and Bin,
On Tue, 2018-10-23 at 13:52 +0800, Rick Chen wrote:
> > > -static void _exit_trap(int code, uint epc, struct pt_regs *regs)
> > > +static void _exit_trap(ulong code, ulong epc, struct pt_regs
> > > *regs)
> > > {
> > > static const char * const exception_code[] = {
> > >
> > -static void _exit_trap(int code, uint epc, struct pt_regs *regs)
> > +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
> > {
> > static const char * const exception_code[] = {
> > "Instruction address misaligned",
> > @@ -70,6 +70,6 @@ static void _e
Hi Lukas,
On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
wrote:
>
> The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
> several places. Fix this.
> In addition, BITS_PER_LONG is set to 64 on RV64I systems.
>
> Signed-off-by: Lukas Auer
> ---
>
> arch/riscv/include/asm/io.h
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.
Signed-off-by: Lukas Auer
---
arch/riscv/include/asm/io.h | 6 +++---
arch/riscv/include/asm/posix_types.h | 6 +++---
arch/riscv
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