Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've notived, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c
The ATUM8548 board didn't appear to set up any tlbs in the
fixed_sdram case; this patch fixes that.
Signed-off-by: Becky Bruce
---
arch/powerpc/cpu/mpc85xx/cpu.c | 58 ++
arch/powerpc/include/asm/fsl_ddr_sdram.h | 13
arch/powerpc/include/asm/fsl_lbc.h |7 ++
board/atum8548/atum8548.c| 25 +
board/freescale/mpc8536ds/mpc8536ds.c| 21 ---
board/freescale/mpc8540ads/mpc8540ads.c | 52 +
board/freescale/mpc8540ads/tlb.c | 19 --
board/freescale/mpc8541cds/mpc8541cds.c | 43 --
board/freescale/mpc8544ds/mpc8544ds.c| 17 --
board/freescale/mpc8548cds/mpc8548cds.c | 38
board/freescale/mpc8555cds/mpc8555cds.c | 45 --
board/freescale/mpc8560ads/mpc8560ads.c | 52 +
board/freescale/mpc8560ads/tlb.c | 19 --
board/freescale/mpc8568mds/mpc8568mds.c | 38
board/freescale/mpc8569mds/mpc8569mds.c | 36
board/freescale/mpc8572ds/mpc8572ds.c| 19 --
board/freescale/p1022ds/p1022ds.c| 13
board/freescale/p1_p2_rdb/ddr.c | 15 +-
board/freescale/p2020ds/p2020ds.c| 34 ++-
board/mpc8540eval/mpc8540eval.c | 52 +
board/pm854/pm854.c | 62 +---
board/pm854/tlb.c| 14 -
board/pm856/pm856.c | 57 +--
board/pm856/tlb.c| 14 -
board/sbc8548/sbc8548.c | 45 +--
board/sbc8548/tlb.c | 34 ---
board/sbc8560/sbc8560.c | 93 +-
board/socrates/sdram.c | 15 +-
board/stx/stxgp3/stxgp3.c| 32 --
board/stx/stxssa/stxssa.c| 33 ---
board/tqc/tqm85xx/sdram.c| 37
board/tqc/tqm85xx/tlb.c | 47 ---
board/xes/common/Makefile|2 -
board/xes/common/fsl_8xxx_ddr.c | 46 ---
board/xes/xpedite517x/xpedite517x.c | 13
include/configs/TQM85xx.h|4 +
36 files changed, 124 insertions(+), 1040 deletions(-)
delete mode 100644 board/xes/common/fsl_8xxx_ddr.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 55ee36d..f242baf 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -286,6 +287,63 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
+/* Common ddr init for non-corenet fsl 85xx platforms */
+#ifndef CONFIG_FSL_CORENET
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int x = 10;
+ unsigned int i;
+
+ /*
+* Work around to stabilize DDR DLL
+*/
+ out_be32(&gur->ddrdllcr, 0x8100);
+ asm("sync;isync;msync");
+ udelay(200);
+ while (in_be32(&gur->ddrdllcr) != 0x81000100) {
+ setbits_be32(&gur->devdisr, 0x0001);
+ for (i = 0; i < x; i++)
+ ;
+ clrbits_be32(&gur->devdisr, 0x0001);
+ x++;
+ }
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x10);
+
