Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-06-12 Thread Tom Rini 
On Sun, Jun 11, 2017 at 11:45:48PM +0200, Andreas Färber wrote:
> Am 12.02.2017 um 15:03 schrieb Marek Vasut:
> > On 02/12/2017 02:24 PM, Andreas Färber wrote:
> >> Am 12.02.2017 um 13:53 schrieb Marek Vasut:
> >>> On 02/12/2017 01:24 PM, Andreas Färber wrote:
>  Am 12.02.2017 um 12:55 schrieb Marek Vasut:
> > On 02/12/2017 12:52 PM, Andreas Färber wrote:
> >> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
> >>
> >>   LD  spl/u-boot-spl
> >> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> >> region `.sram'
> >> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> >> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
> >> make[2]: *** [spl/u-boot-spl] Error 1
> >> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
> >> 'spl/u-boot-spl' failed
> >> make[1]: *** [spl/u-boot-spl] Error 2
> >> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
> >> Makefile:150: recipe for target 'sub-make' failed
> >> make: *** [sub-make] Error 2
> >>
> >> I've reviewed all SPL Kconfig options and found three seemingly 
> >> unneeded
> >> options defaulting to y, but I did not find a way to get this number
> >> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 
> >> was
> >> even worse (~748).
>  I'm looking into a gcc7 package next, but that'll take a bit.
> >>>
> >>> I don't think that's gonna help with U-Boot's bloat. [...]
> >>
> >> Yeah, slightly down with GCC 7.0.1, but not much:
> > 
> > Right, it's the new bloat ...
> > 
> >>   LD  spl/u-boot-spl
> >> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> >> region `.sram'
> >> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 264 bytes
> >> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
> >> make[2]: *** [spl/u-boot-spl] Error 1
> >> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
> >> 'spl/u-boot-spl' failed
> >> make[1]: *** [spl/u-boot-spl] Error 2
> >> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
> >> Makefile:150: recipe for target 'sub-make' failed
> >> make: *** [sub-make] Error 2
> 
> Update: I've rebased the patchset to latest master
> (8cb3ce64f936f5dedbcfc1935c5caf31bb682474 / "Merge
> git://git.denx.de/u-boot-dm") - BMIPS caused trivial conflicts, and DM
> API changes needed to be accounted for.
> 
> https://github.com/afaerber/u-boot/commits/ci20
> 
> By further disabling CONFIG_SPL_RAW_IMAGE_SUPPORT in the ci20 defconfig
> I am now at 344 bytes overflow (gcc 7.1.1):
> 
>   LD  spl/u-boot-spl
> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> region `.sram'
> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 344 bytes
> ../scripts/Makefile.spl:333: recipe for target 'spl/u-boot-spl' failed
> make[2]: *** [spl/u-boot-spl] Error 1
> /home/andreas/OBS/u-boot/Makefile:1382: recipe for target
> 'spl/u-boot-spl' failed
> make[1]: *** [spl/u-boot-spl] Error 2
> 
> By disabling SPL GPIO support and hardcoding a board revision instead of
> detecting it via GPIOs, I can get it down to 80 bytes.
> 
> By aggressively adding #ifndef CONFIG_SPL_BUILD in ci20.c I'm down to 64
> bytes, but not sure if some of that is actually needed for SPL...
> 
> Tom, do you see a chance of merging any of the drivers without the whole
> board building, so that we can reduce the rebasing work and get a common
> base for optimizing?

Yes, I would be agreeable to that, especially if say they can be enabled
also on qemu-mips so we have build but not run time testing and thus
aren't adding dead code.

-- 
Tom


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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-06-11 Thread Andreas Färber 
Am 12.02.2017 um 15:03 schrieb Marek Vasut:
> On 02/12/2017 02:24 PM, Andreas Färber wrote:
>> Am 12.02.2017 um 13:53 schrieb Marek Vasut:
>>> On 02/12/2017 01:24 PM, Andreas Färber wrote:
 Am 12.02.2017 um 12:55 schrieb Marek Vasut:
> On 02/12/2017 12:52 PM, Andreas Färber wrote:
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
>>
>>   LD  spl/u-boot-spl
>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>> region `.sram'
>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
>> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
>> make[2]: *** [spl/u-boot-spl] Error 1
>> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
>> 'spl/u-boot-spl' failed
>> make[1]: *** [spl/u-boot-spl] Error 2
>> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
>> Makefile:150: recipe for target 'sub-make' failed
>> make: *** [sub-make] Error 2
>>
>> I've reviewed all SPL Kconfig options and found three seemingly unneeded
>> options defaulting to y, but I did not find a way to get this number
>> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
>> even worse (~748).
 I'm looking into a gcc7 package next, but that'll take a bit.
>>>
>>> I don't think that's gonna help with U-Boot's bloat. [...]
>>
>> Yeah, slightly down with GCC 7.0.1, but not much:
> 
> Right, it's the new bloat ...
> 
>>   LD  spl/u-boot-spl
>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>> region `.sram'
>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 264 bytes
>> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
>> make[2]: *** [spl/u-boot-spl] Error 1
>> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
>> 'spl/u-boot-spl' failed
>> make[1]: *** [spl/u-boot-spl] Error 2
>> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
>> Makefile:150: recipe for target 'sub-make' failed
>> make: *** [sub-make] Error 2

Update: I've rebased the patchset to latest master
(8cb3ce64f936f5dedbcfc1935c5caf31bb682474 / "Merge
git://git.denx.de/u-boot-dm") - BMIPS caused trivial conflicts, and DM
API changes needed to be accounted for.

https://github.com/afaerber/u-boot/commits/ci20

By further disabling CONFIG_SPL_RAW_IMAGE_SUPPORT in the ci20 defconfig
I am now at 344 bytes overflow (gcc 7.1.1):

  LD  spl/u-boot-spl
mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
region `.sram'
mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 344 bytes
../scripts/Makefile.spl:333: recipe for target 'spl/u-boot-spl' failed
make[2]: *** [spl/u-boot-spl] Error 1
/home/andreas/OBS/u-boot/Makefile:1382: recipe for target
'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 2

By disabling SPL GPIO support and hardcoding a board revision instead of
detecting it via GPIOs, I can get it down to 80 bytes.

By aggressively adding #ifndef CONFIG_SPL_BUILD in ci20.c I'm down to 64
bytes, but not sure if some of that is actually needed for SPL...

Tom, do you see a chance of merging any of the drivers without the whole
board building, so that we can reduce the rebasing work and get a common
base for optimizing?

Regards,
Andreas

-- 
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GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-15 Thread Marek Vasut 
On 02/15/2017 10:50 PM, Tom Rini wrote:
> On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote:
>> On 02/15/2017 12:11 AM, Tom Rini wrote:
>>> On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
 On 02/14/2017 11:58 PM, Tom Rini wrote:
> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
>> Hi Marek,
>>
>> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
>>> From: Paul Burton 
>>>
>>> Add support for the Creator CI20 platform based on the JZ4780 SoC.
>>> The DTS file comes from Linux 4.6 as of revision
>>> 78800558d104e003f9ae92e0107f1de39cf9de9f
>>>
>>> So far, there are still a few details which will have to be fixed
>>> once they are fleshed out in Linux:
>>> - pinmux: Thus far, this board just pokes the pinmux registers to
>>>   set the pinmux. For MMC in SPL, this will have to stay.
>>>   But for full u-boot a proper pinmux driver will have to
>>>   be added once the pinmux semantics in DT are in mainline
>>>   Linux.
>>> - ethernet,efuse: DT bindings are missing from mainline Linux.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Daniel Schwierzeck 
>>> Cc: Paul Burton 
>>> ---
>>>  arch/mips/dts/Makefile|   1 +
>>>  arch/mips/dts/ci20.dts| 114 ++
>>>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>>>  board/imgtec/ci20/Kconfig |  35 +
>>>  board/imgtec/ci20/Makefile|   5 +
>>>  board/imgtec/ci20/README  |  10 ++
>>>  board/imgtec/ci20/ci20.c  | 354 
>>> ++
>>>  configs/ci20_defconfig|  28 
>>>  include/configs/ci20.h| 105 +
>>>  9 files changed, 663 insertions(+)
>>>  create mode 100644 arch/mips/dts/ci20.dts
>>>  create mode 100644 board/imgtec/ci20/Kconfig
>>>  create mode 100644 board/imgtec/ci20/Makefile
>>>  create mode 100644 board/imgtec/ci20/README
>>>  create mode 100644 board/imgtec/ci20/ci20.c
>>>  create mode 100644 configs/ci20_defconfig
>>>  create mode 100644 include/configs/ci20.h
>>
>> I've looked into testing the remainder of this patchset, not seeing a
>> newer version. You can find my branch here:
>>
>> https://github.com/afaerber/u-boot/commits/ci20
> [snip]
>>   LD  spl/u-boot-spl
>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>> region `.sram'
>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
>
> I can recreate that too here real quick, but can't test out changes on
> my Ci20 right now.  Can you try:
>
> diff --git a/include/configs/ci20.h b/include/configs/ci20.h
> index 4503adb..9e2ad7b 100644
> --- a/include/configs/ci20.h
> +++ b/include/configs/ci20.h
> @@ -70,10 +70,10 @@
>  /* SPL */
>  #define CONFIG_SPL_FRAMEWORK
>  
> -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
> +#define CONFIG_SPL_STACK 0xf4008200 /* only max. 1.5KB spare! */
>  
>  #define CONFIG_SPL_TEXT_BASE 0xf4000a00
> -#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0xa00)
> +#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0x800)

 This will not work, the stack is configured at it's limit already.

>  #define CONFIG_SPL_BSS_START_ADDR0xf4004000
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x2000 /* 512KB, arbitrary 
> */
>
>
> Now, off the top of my head I'm only giving myself a 50/50 chance of
> having moved the stack address in the correct direction.  And note that
> I don't know why we say only max of 2KB for stack, and then ensure we
> have 2.5KB of room, but I've shifted 512 bytes from one side to the
> other.  And it's quite probable that we should make use having SPL stack
> get moved into DDR

 You mean the DDR which you init in the SPL ? :)
>>>
>>> Yes, I mean the DDR which we init in the SPL, after we've init'd it, so
>>> that we can work more comfortably in cramped and constrained spaces.
>>
>> You know, you are still limited by the 14 kiB load limit of the BootROM.
>> I think there's more than 16 kiB of SRAM total, so there's no real
>> problem with the stack. The problem is that 14 kiB load limit of the
>> BootROM, it will NOT LOAD MORE than 14 kiB of code . I tried (because,
>> well, 14 kiB is too small). IT DOES NOT WORK.
> 
> Can we use those last 2KiB of SRAM for our stack or does that freak out
> the BootROM?

IIRC I tried pretty much everything to squeeze more space out of this
chip and this is the only thing that worked.

> If so, we should tweak the above definitions to set the
> hard limit at 14 * SZ_1K and put stack at 0xf4004200 ?

Be my guest, research the hell out of this

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-15 Thread Tom Rini 
On Wed, Feb 15, 2017 at 09:46:38PM +0100, Marek Vasut wrote:
> On 02/15/2017 12:11 AM, Tom Rini wrote:
> > On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
> >> On 02/14/2017 11:58 PM, Tom Rini wrote:
> >>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
>  Hi Marek,
> 
>  Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> > From: Paul Burton 
> >
> > Add support for the Creator CI20 platform based on the JZ4780 SoC.
> > The DTS file comes from Linux 4.6 as of revision
> > 78800558d104e003f9ae92e0107f1de39cf9de9f
> >
> > So far, there are still a few details which will have to be fixed
> > once they are fleshed out in Linux:
> > - pinmux: Thus far, this board just pokes the pinmux registers to
> >   set the pinmux. For MMC in SPL, this will have to stay.
> >   But for full u-boot a proper pinmux driver will have to
> >   be added once the pinmux semantics in DT are in mainline
> >   Linux.
> > - ethernet,efuse: DT bindings are missing from mainline Linux.
> >
> > Signed-off-by: Marek Vasut 
> > Cc: Daniel Schwierzeck 
> > Cc: Paul Burton 
> > ---
> >  arch/mips/dts/Makefile|   1 +
> >  arch/mips/dts/ci20.dts| 114 ++
> >  arch/mips/mach-jz47xx/Kconfig |  11 ++
> >  board/imgtec/ci20/Kconfig |  35 +
> >  board/imgtec/ci20/Makefile|   5 +
> >  board/imgtec/ci20/README  |  10 ++
> >  board/imgtec/ci20/ci20.c  | 354 
> > ++
> >  configs/ci20_defconfig|  28 
> >  include/configs/ci20.h| 105 +
> >  9 files changed, 663 insertions(+)
> >  create mode 100644 arch/mips/dts/ci20.dts
> >  create mode 100644 board/imgtec/ci20/Kconfig
> >  create mode 100644 board/imgtec/ci20/Makefile
> >  create mode 100644 board/imgtec/ci20/README
> >  create mode 100644 board/imgtec/ci20/ci20.c
> >  create mode 100644 configs/ci20_defconfig
> >  create mode 100644 include/configs/ci20.h
> 
>  I've looked into testing the remainder of this patchset, not seeing a
>  newer version. You can find my branch here:
> 
>  https://github.com/afaerber/u-boot/commits/ci20
> >>> [snip]
>    LD  spl/u-boot-spl
>  mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>  region `.sram'
>  mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> >>>
> >>> I can recreate that too here real quick, but can't test out changes on
> >>> my Ci20 right now.  Can you try:
> >>>
> >>> diff --git a/include/configs/ci20.h b/include/configs/ci20.h
> >>> index 4503adb..9e2ad7b 100644
> >>> --- a/include/configs/ci20.h
> >>> +++ b/include/configs/ci20.h
> >>> @@ -70,10 +70,10 @@
> >>>  /* SPL */
> >>>  #define CONFIG_SPL_FRAMEWORK
> >>>  
> >>> -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
> >>> +#define CONFIG_SPL_STACK 0xf4008200 /* only max. 1.5KB spare! */
> >>>  
> >>>  #define CONFIG_SPL_TEXT_BASE 0xf4000a00
> >>> -#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0xa00)
> >>> +#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0x800)
> >>
> >> This will not work, the stack is configured at it's limit already.
> >>
> >>>  #define CONFIG_SPL_BSS_START_ADDR0xf4004000
> >>>  #define CONFIG_SPL_BSS_MAX_SIZE  0x2000 /* 512KB, arbitrary 
> >>> */
> >>>
> >>>
> >>> Now, off the top of my head I'm only giving myself a 50/50 chance of
> >>> having moved the stack address in the correct direction.  And note that
> >>> I don't know why we say only max of 2KB for stack, and then ensure we
> >>> have 2.5KB of room, but I've shifted 512 bytes from one side to the
> >>> other.  And it's quite probable that we should make use having SPL stack
> >>> get moved into DDR
> >>
> >> You mean the DDR which you init in the SPL ? :)
> > 
> > Yes, I mean the DDR which we init in the SPL, after we've init'd it, so
> > that we can work more comfortably in cramped and constrained spaces.
> 
> You know, you are still limited by the 14 kiB load limit of the BootROM.
> I think there's more than 16 kiB of SRAM total, so there's no real
> problem with the stack. The problem is that 14 kiB load limit of the
> BootROM, it will NOT LOAD MORE than 14 kiB of code . I tried (because,
> well, 14 kiB is too small). IT DOES NOT WORK.

Can we use those last 2KiB of SRAM for our stack or does that freak out
the BootROM?  If so, we should tweak the above definitions to set the
hard limit at 14 * SZ_1K and put stack at 0xf4004200 ?  Where is
0xf4008000 in the memory map?

> >>> , but I don't have the memory map handy either (and
> >>> based on the above snippets I'm confused as CONFIG_SPL_BSS_START_ADDR
> >>> should be in DDR space, I don't know

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-15 Thread Marek Vasut 
On 02/15/2017 12:11 AM, Tom Rini wrote:
> On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
>> On 02/14/2017 11:58 PM, Tom Rini wrote:
>>> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
 Hi Marek,

 Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> From: Paul Burton 
>
> Add support for the Creator CI20 platform based on the JZ4780 SoC.
> The DTS file comes from Linux 4.6 as of revision
> 78800558d104e003f9ae92e0107f1de39cf9de9f
>
> So far, there are still a few details which will have to be fixed
> once they are fleshed out in Linux:
> - pinmux: Thus far, this board just pokes the pinmux registers to
>   set the pinmux. For MMC in SPL, this will have to stay.
> But for full u-boot a proper pinmux driver will have to
> be added once the pinmux semantics in DT are in mainline
> Linux.
> - ethernet,efuse: DT bindings are missing from mainline Linux.
>
> Signed-off-by: Marek Vasut 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  arch/mips/dts/Makefile|   1 +
>  arch/mips/dts/ci20.dts| 114 ++
>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>  board/imgtec/ci20/Kconfig |  35 +
>  board/imgtec/ci20/Makefile|   5 +
>  board/imgtec/ci20/README  |  10 ++
>  board/imgtec/ci20/ci20.c  | 354 
> ++
>  configs/ci20_defconfig|  28 
>  include/configs/ci20.h| 105 +
>  9 files changed, 663 insertions(+)
>  create mode 100644 arch/mips/dts/ci20.dts
>  create mode 100644 board/imgtec/ci20/Kconfig
>  create mode 100644 board/imgtec/ci20/Makefile
>  create mode 100644 board/imgtec/ci20/README
>  create mode 100644 board/imgtec/ci20/ci20.c
>  create mode 100644 configs/ci20_defconfig
>  create mode 100644 include/configs/ci20.h

 I've looked into testing the remainder of this patchset, not seeing a
 newer version. You can find my branch here:

 https://github.com/afaerber/u-boot/commits/ci20
>>> [snip]
   LD  spl/u-boot-spl
 mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
 region `.sram'
 mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
>>>
>>> I can recreate that too here real quick, but can't test out changes on
>>> my Ci20 right now.  Can you try:
>>>
>>> diff --git a/include/configs/ci20.h b/include/configs/ci20.h
>>> index 4503adb..9e2ad7b 100644
>>> --- a/include/configs/ci20.h
>>> +++ b/include/configs/ci20.h
>>> @@ -70,10 +70,10 @@
>>>  /* SPL */
>>>  #define CONFIG_SPL_FRAMEWORK
>>>  
>>> -#define CONFIG_SPL_STACK   0xf4008000 /* only max. 2KB spare! */
>>> +#define CONFIG_SPL_STACK   0xf4008200 /* only max. 1.5KB spare! */
>>>  
>>>  #define CONFIG_SPL_TEXT_BASE   0xf4000a00
>>> -#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0xa00)
>>> +#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0x800)
>>
>> This will not work, the stack is configured at it's limit already.
>>
>>>  #define CONFIG_SPL_BSS_START_ADDR  0xf4004000
>>>  #define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 512KB, arbitrary 
>>> */
>>>
>>>
>>> Now, off the top of my head I'm only giving myself a 50/50 chance of
>>> having moved the stack address in the correct direction.  And note that
>>> I don't know why we say only max of 2KB for stack, and then ensure we
>>> have 2.5KB of room, but I've shifted 512 bytes from one side to the
>>> other.  And it's quite probable that we should make use having SPL stack
>>> get moved into DDR
>>
>> You mean the DDR which you init in the SPL ? :)
> 
> Yes, I mean the DDR which we init in the SPL, after we've init'd it, so
> that we can work more comfortably in cramped and constrained spaces.

You know, you are still limited by the 14 kiB load limit of the BootROM.
I think there's more than 16 kiB of SRAM total, so there's no real
problem with the stack. The problem is that 14 kiB load limit of the
BootROM, it will NOT LOAD MORE than 14 kiB of code . I tried (because,
well, 14 kiB is too small). IT DOES NOT WORK.

>>> , but I don't have the memory map handy either (and
>>> based on the above snippets I'm confused as CONFIG_SPL_BSS_START_ADDR
>>> should be in DDR space, I don't know if internal memory directly follows
>>> into DDR here or what).
>>>
>>> I do want to reiterate that I am eager to have Ci20 be working in
>>> mainline as I have one and I want to figure out how to include it in my
>>> farm, or at least manual testing from time to time.  Thanks!
>>
>> Well, these patches were rotting on the list for year or so without
>> getting any attention, until the point I had to scream on the IRC to get
>> ANY review comments, multiple times, so I really see a lot of interest
>> in

Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-14 Thread Tom Rini 
On Wed, Feb 15, 2017 at 12:03:32AM +0100, Marek Vasut wrote:
> On 02/14/2017 11:58 PM, Tom Rini wrote:
> > On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
> >> Hi Marek,
> >>
> >> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> >>> From: Paul Burton 
> >>>
> >>> Add support for the Creator CI20 platform based on the JZ4780 SoC.
> >>> The DTS file comes from Linux 4.6 as of revision
> >>> 78800558d104e003f9ae92e0107f1de39cf9de9f
> >>>
> >>> So far, there are still a few details which will have to be fixed
> >>> once they are fleshed out in Linux:
> >>> - pinmux: Thus far, this board just pokes the pinmux registers to
> >>>   set the pinmux. For MMC in SPL, this will have to stay.
> >>> But for full u-boot a proper pinmux driver will have to
> >>> be added once the pinmux semantics in DT are in mainline
> >>> Linux.
> >>> - ethernet,efuse: DT bindings are missing from mainline Linux.
> >>>
> >>> Signed-off-by: Marek Vasut 
> >>> Cc: Daniel Schwierzeck 
> >>> Cc: Paul Burton 
> >>> ---
> >>>  arch/mips/dts/Makefile|   1 +
> >>>  arch/mips/dts/ci20.dts| 114 ++
> >>>  arch/mips/mach-jz47xx/Kconfig |  11 ++
> >>>  board/imgtec/ci20/Kconfig |  35 +
> >>>  board/imgtec/ci20/Makefile|   5 +
> >>>  board/imgtec/ci20/README  |  10 ++
> >>>  board/imgtec/ci20/ci20.c  | 354 
> >>> ++
> >>>  configs/ci20_defconfig|  28 
> >>>  include/configs/ci20.h| 105 +
> >>>  9 files changed, 663 insertions(+)
> >>>  create mode 100644 arch/mips/dts/ci20.dts
> >>>  create mode 100644 board/imgtec/ci20/Kconfig
> >>>  create mode 100644 board/imgtec/ci20/Makefile
> >>>  create mode 100644 board/imgtec/ci20/README
> >>>  create mode 100644 board/imgtec/ci20/ci20.c
> >>>  create mode 100644 configs/ci20_defconfig
> >>>  create mode 100644 include/configs/ci20.h
> >>
> >> I've looked into testing the remainder of this patchset, not seeing a
> >> newer version. You can find my branch here:
> >>
> >> https://github.com/afaerber/u-boot/commits/ci20
> > [snip]
> >>   LD  spl/u-boot-spl
> >> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> >> region `.sram'
> >> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> > 
> > I can recreate that too here real quick, but can't test out changes on
> > my Ci20 right now.  Can you try:
> > 
> > diff --git a/include/configs/ci20.h b/include/configs/ci20.h
> > index 4503adb..9e2ad7b 100644
> > --- a/include/configs/ci20.h
> > +++ b/include/configs/ci20.h
> > @@ -70,10 +70,10 @@
> >  /* SPL */
> >  #define CONFIG_SPL_FRAMEWORK
> >  
> > -#define CONFIG_SPL_STACK   0xf4008000 /* only max. 2KB spare! */
> > +#define CONFIG_SPL_STACK   0xf4008200 /* only max. 1.5KB spare! */
> >  
> >  #define CONFIG_SPL_TEXT_BASE   0xf4000a00
> > -#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0xa00)
> > +#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0x800)
> 
> This will not work, the stack is configured at it's limit already.
> 
> >  #define CONFIG_SPL_BSS_START_ADDR  0xf4004000
> >  #define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 512KB, arbitrary 
> > */
> > 
> > 
> > Now, off the top of my head I'm only giving myself a 50/50 chance of
> > having moved the stack address in the correct direction.  And note that
> > I don't know why we say only max of 2KB for stack, and then ensure we
> > have 2.5KB of room, but I've shifted 512 bytes from one side to the
> > other.  And it's quite probable that we should make use having SPL stack
> > get moved into DDR
> 
> You mean the DDR which you init in the SPL ? :)

Yes, I mean the DDR which we init in the SPL, after we've init'd it, so
that we can work more comfortably in cramped and constrained spaces.

> >, but I don't have the memory map handy either (and
> > based on the above snippets I'm confused as CONFIG_SPL_BSS_START_ADDR
> > should be in DDR space, I don't know if internal memory directly follows
> > into DDR here or what).
> > 
> > I do want to reiterate that I am eager to have Ci20 be working in
> > mainline as I have one and I want to figure out how to include it in my
> > farm, or at least manual testing from time to time.  Thanks!
> 
> Well, these patches were rotting on the list for year or so without
> getting any attention, until the point I had to scream on the IRC to get
> ANY review comments, multiple times, so I really see a lot of interest
> in getting this in, indeed :)

Yeah, I feel bad about not having more time for all of the various
things I'd like to see happen, happen.  But that's why I bought the Ci20
and Ci40 (and some other boards) as a regular person rather than try and
get a freebie.

-- 
Tom


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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-14 Thread Marek Vasut 
On 02/14/2017 11:58 PM, Tom Rini wrote:
> On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
>> Hi Marek,
>>
>> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
>>> From: Paul Burton 
>>>
>>> Add support for the Creator CI20 platform based on the JZ4780 SoC.
>>> The DTS file comes from Linux 4.6 as of revision
>>> 78800558d104e003f9ae92e0107f1de39cf9de9f
>>>
>>> So far, there are still a few details which will have to be fixed
>>> once they are fleshed out in Linux:
>>> - pinmux: Thus far, this board just pokes the pinmux registers to
>>>   set the pinmux. For MMC in SPL, this will have to stay.
>>>   But for full u-boot a proper pinmux driver will have to
>>>   be added once the pinmux semantics in DT are in mainline
>>>   Linux.
>>> - ethernet,efuse: DT bindings are missing from mainline Linux.
>>>
>>> Signed-off-by: Marek Vasut 
>>> Cc: Daniel Schwierzeck 
>>> Cc: Paul Burton 
>>> ---
>>>  arch/mips/dts/Makefile|   1 +
>>>  arch/mips/dts/ci20.dts| 114 ++
>>>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>>>  board/imgtec/ci20/Kconfig |  35 +
>>>  board/imgtec/ci20/Makefile|   5 +
>>>  board/imgtec/ci20/README  |  10 ++
>>>  board/imgtec/ci20/ci20.c  | 354 
>>> ++
>>>  configs/ci20_defconfig|  28 
>>>  include/configs/ci20.h| 105 +
>>>  9 files changed, 663 insertions(+)
>>>  create mode 100644 arch/mips/dts/ci20.dts
>>>  create mode 100644 board/imgtec/ci20/Kconfig
>>>  create mode 100644 board/imgtec/ci20/Makefile
>>>  create mode 100644 board/imgtec/ci20/README
>>>  create mode 100644 board/imgtec/ci20/ci20.c
>>>  create mode 100644 configs/ci20_defconfig
>>>  create mode 100644 include/configs/ci20.h
>>
>> I've looked into testing the remainder of this patchset, not seeing a
>> newer version. You can find my branch here:
>>
>> https://github.com/afaerber/u-boot/commits/ci20
> [snip]
>>   LD  spl/u-boot-spl
>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>> region `.sram'
>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> 
> I can recreate that too here real quick, but can't test out changes on
> my Ci20 right now.  Can you try:
> 
> diff --git a/include/configs/ci20.h b/include/configs/ci20.h
> index 4503adb..9e2ad7b 100644
> --- a/include/configs/ci20.h
> +++ b/include/configs/ci20.h
> @@ -70,10 +70,10 @@
>  /* SPL */
>  #define CONFIG_SPL_FRAMEWORK
>  
> -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
> +#define CONFIG_SPL_STACK 0xf4008200 /* only max. 1.5KB spare! */
>  
>  #define CONFIG_SPL_TEXT_BASE 0xf4000a00
> -#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0xa00)
> +#define CONFIG_SPL_MAX_SIZE  ((14 * 1024) - 0x800)

This will not work, the stack is configured at it's limit already.

>  #define CONFIG_SPL_BSS_START_ADDR0xf4004000
>  #define CONFIG_SPL_BSS_MAX_SIZE  0x2000 /* 512KB, arbitrary 
> */
> 
> 
> Now, off the top of my head I'm only giving myself a 50/50 chance of
> having moved the stack address in the correct direction.  And note that
> I don't know why we say only max of 2KB for stack, and then ensure we
> have 2.5KB of room, but I've shifted 512 bytes from one side to the
> other.  And it's quite probable that we should make use having SPL stack
> get moved into DDR

You mean the DDR which you init in the SPL ? :)

>, but I don't have the memory map handy either (and
> based on the above snippets I'm confused as CONFIG_SPL_BSS_START_ADDR
> should be in DDR space, I don't know if internal memory directly follows
> into DDR here or what).
> 
> I do want to reiterate that I am eager to have Ci20 be working in
> mainline as I have one and I want to figure out how to include it in my
> farm, or at least manual testing from time to time.  Thanks!

Well, these patches were rotting on the list for year or so without
getting any attention, until the point I had to scream on the IRC to get
ANY review comments, multiple times, so I really see a lot of interest
in getting this in, indeed :)

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-14 Thread Tom Rini 
On Sun, Feb 12, 2017 at 12:52:45PM +0100, Andreas Färber wrote:
> Hi Marek,
> 
> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> > From: Paul Burton 
> > 
> > Add support for the Creator CI20 platform based on the JZ4780 SoC.
> > The DTS file comes from Linux 4.6 as of revision
> > 78800558d104e003f9ae92e0107f1de39cf9de9f
> > 
> > So far, there are still a few details which will have to be fixed
> > once they are fleshed out in Linux:
> > - pinmux: Thus far, this board just pokes the pinmux registers to
> >   set the pinmux. For MMC in SPL, this will have to stay.
> >   But for full u-boot a proper pinmux driver will have to
> >   be added once the pinmux semantics in DT are in mainline
> >   Linux.
> > - ethernet,efuse: DT bindings are missing from mainline Linux.
> > 
> > Signed-off-by: Marek Vasut 
> > Cc: Daniel Schwierzeck 
> > Cc: Paul Burton 
> > ---
> >  arch/mips/dts/Makefile|   1 +
> >  arch/mips/dts/ci20.dts| 114 ++
> >  arch/mips/mach-jz47xx/Kconfig |  11 ++
> >  board/imgtec/ci20/Kconfig |  35 +
> >  board/imgtec/ci20/Makefile|   5 +
> >  board/imgtec/ci20/README  |  10 ++
> >  board/imgtec/ci20/ci20.c  | 354 
> > ++
> >  configs/ci20_defconfig|  28 
> >  include/configs/ci20.h| 105 +
> >  9 files changed, 663 insertions(+)
> >  create mode 100644 arch/mips/dts/ci20.dts
> >  create mode 100644 board/imgtec/ci20/Kconfig
> >  create mode 100644 board/imgtec/ci20/Makefile
> >  create mode 100644 board/imgtec/ci20/README
> >  create mode 100644 board/imgtec/ci20/ci20.c
> >  create mode 100644 configs/ci20_defconfig
> >  create mode 100644 include/configs/ci20.h
> 
> I've looked into testing the remainder of this patchset, not seeing a
> newer version. You can find my branch here:
> 
> https://github.com/afaerber/u-boot/commits/ci20
[snip]
>   LD  spl/u-boot-spl
> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> region `.sram'
> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes

I can recreate that too here real quick, but can't test out changes on
my Ci20 right now.  Can you try:

diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index 4503adb..9e2ad7b 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -70,10 +70,10 @@
 /* SPL */
 #define CONFIG_SPL_FRAMEWORK
 
-#define CONFIG_SPL_STACK   0xf4008000 /* only max. 2KB spare! */
+#define CONFIG_SPL_STACK   0xf4008200 /* only max. 1.5KB spare! */
 
 #define CONFIG_SPL_TEXT_BASE   0xf4000a00
-#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0xa00)
+#define CONFIG_SPL_MAX_SIZE((14 * 1024) - 0x800)
 
 #define CONFIG_SPL_BSS_START_ADDR  0xf4004000
 #define CONFIG_SPL_BSS_MAX_SIZE0x2000 /* 512KB, arbitrary 
*/


Now, off the top of my head I'm only giving myself a 50/50 chance of
having moved the stack address in the correct direction.  And note that
I don't know why we say only max of 2KB for stack, and then ensure we
have 2.5KB of room, but I've shifted 512 bytes from one side to the
other.  And it's quite probable that we should make use having SPL stack
get moved into DDR, but I don't have the memory map handy either (and
based on the above snippets I'm confused as CONFIG_SPL_BSS_START_ADDR
should be in DDR space, I don't know if internal memory directly follows
into DDR here or what).

I do want to reiterate that I am eager to have Ci20 be working in
mainline as I have one and I want to figure out how to include it in my
farm, or at least manual testing from time to time.  Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Andreas Färber 
Am 12.02.2017 um 12:52 schrieb Andreas Färber:
> Hi Marek,
> 
> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
>> From: Paul Burton 
>>
>> Add support for the Creator CI20 platform based on the JZ4780 SoC.
>> The DTS file comes from Linux 4.6 as of revision
>> 78800558d104e003f9ae92e0107f1de39cf9de9f
>>
>> So far, there are still a few details which will have to be fixed
>> once they are fleshed out in Linux:
>> - pinmux: Thus far, this board just pokes the pinmux registers to
>>   set the pinmux. For MMC in SPL, this will have to stay.
>>But for full u-boot a proper pinmux driver will have to
>>be added once the pinmux semantics in DT are in mainline
>>Linux.
>> - ethernet,efuse: DT bindings are missing from mainline Linux.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  arch/mips/dts/Makefile|   1 +
>>  arch/mips/dts/ci20.dts| 114 ++
>>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>>  board/imgtec/ci20/Kconfig |  35 +
>>  board/imgtec/ci20/Makefile|   5 +
>>  board/imgtec/ci20/README  |  10 ++
>>  board/imgtec/ci20/ci20.c  | 354 
>> ++
>>  configs/ci20_defconfig|  28 
>>  include/configs/ci20.h| 105 +
>>  9 files changed, 663 insertions(+)
>>  create mode 100644 arch/mips/dts/ci20.dts
>>  create mode 100644 board/imgtec/ci20/Kconfig
>>  create mode 100644 board/imgtec/ci20/Makefile
>>  create mode 100644 board/imgtec/ci20/README
>>  create mode 100644 board/imgtec/ci20/ci20.c
>>  create mode 100644 configs/ci20_defconfig
>>  create mode 100644 include/configs/ci20.h
> 
> I've looked into testing the remainder of this patchset, not seeing a
> newer version. You can find my branch here:
> 
> https://github.com/afaerber/u-boot/commits/ci20
> 
> In particular I fixed the MMC set_ios signature to silence a warning
> about the int vs. void return type, which I intend to clean up and submit.

Erm, I realized that the MMC driver is among the patches not yet merged,
so it'll have to be fixed in the next respin.

Regards,
Andreas

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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Marek Vasut 
On 02/12/2017 02:24 PM, Andreas Färber wrote:
> Am 12.02.2017 um 13:53 schrieb Marek Vasut:
>> On 02/12/2017 01:24 PM, Andreas Färber wrote:
>>> Am 12.02.2017 um 12:55 schrieb Marek Vasut:
 On 02/12/2017 12:52 PM, Andreas Färber wrote:
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
>
>   LD  spl/u-boot-spl
> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> region `.sram'
> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
> make[2]: *** [spl/u-boot-spl] Error 1
> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
> 'spl/u-boot-spl' failed
> make[1]: *** [spl/u-boot-spl] Error 2
> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
> Makefile:150: recipe for target 'sub-make' failed
> make: *** [sub-make] Error 2
>
> I've reviewed all SPL Kconfig options and found three seemingly unneeded
> options defaulting to y, but I did not find a way to get this number
> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
> even worse (~748).

 The recommended one was gcc 6.x , [...]
>>>
>>> http://elinux.org/CI20_Dev_Zone#Toolchain
>>>
>>> eLinux.org recommends a 2013.11 CodeSourcery toolchain with gcc 4.8.1:
>>
>> Well probably for some ancient vendoruboot ;-)
> 
> v2013.10 based. ;-)

Well, that's still reasonably recent for a vendoruboot on mips ...

>>> "For compiling u-boot, please use this. u-boot first stage spl has a
>>> size limitation.
>>> And this toolchain manages to generate a binary that is just within the
>>> limit."
>>>
>>> Sadly it isn't.
>>>
>>> I'm looking into a gcc7 package next, but that'll take a bit.
>>
>> I don't think that's gonna help with U-Boot's bloat. [...]
> 
> Yeah, slightly down with GCC 7.0.1, but not much:

Right, it's the new bloat ...

>   LD  spl/u-boot-spl
> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> region `.sram'
> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 264 bytes
> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
> make[2]: *** [spl/u-boot-spl] Error 1
> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
> 'spl/u-boot-spl' failed
> make[1]: *** [spl/u-boot-spl] Error 2
> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
> Makefile:150: recipe for target 'sub-make' failed
> make: *** [sub-make] Error 2
> 
> Cheers,
> Andreas
> 


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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Andreas Färber 
Am 12.02.2017 um 13:53 schrieb Marek Vasut:
> On 02/12/2017 01:24 PM, Andreas Färber wrote:
>> Am 12.02.2017 um 12:55 schrieb Marek Vasut:
>>> On 02/12/2017 12:52 PM, Andreas Färber wrote:
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:

   LD  spl/u-boot-spl
 mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
 region `.sram'
 mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
 ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
 make[2]: *** [spl/u-boot-spl] Error 1
 /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
 'spl/u-boot-spl' failed
 make[1]: *** [spl/u-boot-spl] Error 2
 make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
 Makefile:150: recipe for target 'sub-make' failed
 make: *** [sub-make] Error 2

 I've reviewed all SPL Kconfig options and found three seemingly unneeded
 options defaulting to y, but I did not find a way to get this number
 down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
 even worse (~748).
>>>
>>> The recommended one was gcc 6.x , [...]
>>
>> http://elinux.org/CI20_Dev_Zone#Toolchain
>>
>> eLinux.org recommends a 2013.11 CodeSourcery toolchain with gcc 4.8.1:
> 
> Well probably for some ancient vendoruboot ;-)

v2013.10 based. ;-)

>> "For compiling u-boot, please use this. u-boot first stage spl has a
>> size limitation.
>> And this toolchain manages to generate a binary that is just within the
>> limit."
>>
>> Sadly it isn't.
>>
>> I'm looking into a gcc7 package next, but that'll take a bit.
> 
> I don't think that's gonna help with U-Boot's bloat. [...]

Yeah, slightly down with GCC 7.0.1, but not much:

  LD  spl/u-boot-spl
mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
region `.sram'
mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 264 bytes
../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
make[2]: *** [spl/u-boot-spl] Error 1
/home/andreas/OBS/u-boot/Makefile:1342: recipe for target
'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 2
make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
Makefile:150: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2

Cheers,
Andreas

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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Marek Vasut 
On 02/12/2017 01:24 PM, Andreas Färber wrote:
> Am 12.02.2017 um 12:55 schrieb Marek Vasut:
>> On 02/12/2017 12:52 PM, Andreas Färber wrote:
>>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
>>>
>>>   LD  spl/u-boot-spl
>>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>>> region `.sram'
>>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
>>> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
>>> make[2]: *** [spl/u-boot-spl] Error 1
>>> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
>>> 'spl/u-boot-spl' failed
>>> make[1]: *** [spl/u-boot-spl] Error 2
>>> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
>>> Makefile:150: recipe for target 'sub-make' failed
>>> make: *** [sub-make] Error 2
>>>
>>> I've reviewed all SPL Kconfig options and found three seemingly unneeded
>>> options defaulting to y, but I did not find a way to get this number
>>> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
>>> even worse (~748).
>>
>> The recommended one was gcc 6.x , [...]
> 
> http://elinux.org/CI20_Dev_Zone#Toolchain
> 
> eLinux.org recommends a 2013.11 CodeSourcery toolchain with gcc 4.8.1:

Well probably for some ancient vendoruboot ;-)

> "For compiling u-boot, please use this. u-boot first stage spl has a
> size limitation.
> And this toolchain manages to generate a binary that is just within the
> limit."
> 
> Sadly it isn't.
> 
> I'm looking into a gcc7 package next, but that'll take a bit.

I don't think that's gonna help with U-Boot's bloat. I had to trim down
a lot of things already (ie. the MMC tinification), but it seems U-Boot
is growing and growing.


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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Andreas Färber 
Am 12.02.2017 um 12:55 schrieb Marek Vasut:
> On 02/12/2017 12:52 PM, Andreas Färber wrote:
>> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
>>
>>   LD  spl/u-boot-spl
>> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
>> region `.sram'
>> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
>> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
>> make[2]: *** [spl/u-boot-spl] Error 1
>> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
>> 'spl/u-boot-spl' failed
>> make[1]: *** [spl/u-boot-spl] Error 2
>> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
>> Makefile:150: recipe for target 'sub-make' failed
>> make: *** [sub-make] Error 2
>>
>> I've reviewed all SPL Kconfig options and found three seemingly unneeded
>> options defaulting to y, but I did not find a way to get this number
>> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
>> even worse (~748).
> 
> The recommended one was gcc 6.x , [...]

http://elinux.org/CI20_Dev_Zone#Toolchain

eLinux.org recommends a 2013.11 CodeSourcery toolchain with gcc 4.8.1:

"For compiling u-boot, please use this. u-boot first stage spl has a
size limitation.
And this toolchain manages to generate a binary that is just within the
limit."

Sadly it isn't.

I'm looking into a gcc7 package next, but that'll take a bit.

Cheers,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Marek Vasut 
On 02/12/2017 12:52 PM, Andreas Färber wrote:
> Hi Marek,

Hi!

> Am 01.12.2016 um 02:06 schrieb Marek Vasut:
>> From: Paul Burton 
>>
>> Add support for the Creator CI20 platform based on the JZ4780 SoC.
>> The DTS file comes from Linux 4.6 as of revision
>> 78800558d104e003f9ae92e0107f1de39cf9de9f
>>
>> So far, there are still a few details which will have to be fixed
>> once they are fleshed out in Linux:
>> - pinmux: Thus far, this board just pokes the pinmux registers to
>>   set the pinmux. For MMC in SPL, this will have to stay.
>>But for full u-boot a proper pinmux driver will have to
>>be added once the pinmux semantics in DT are in mainline
>>Linux.
>> - ethernet,efuse: DT bindings are missing from mainline Linux.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  arch/mips/dts/Makefile|   1 +
>>  arch/mips/dts/ci20.dts| 114 ++
>>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>>  board/imgtec/ci20/Kconfig |  35 +
>>  board/imgtec/ci20/Makefile|   5 +
>>  board/imgtec/ci20/README  |  10 ++
>>  board/imgtec/ci20/ci20.c  | 354 
>> ++
>>  configs/ci20_defconfig|  28 
>>  include/configs/ci20.h| 105 +
>>  9 files changed, 663 insertions(+)
>>  create mode 100644 arch/mips/dts/ci20.dts
>>  create mode 100644 board/imgtec/ci20/Kconfig
>>  create mode 100644 board/imgtec/ci20/Makefile
>>  create mode 100644 board/imgtec/ci20/README
>>  create mode 100644 board/imgtec/ci20/ci20.c
>>  create mode 100644 configs/ci20_defconfig
>>  create mode 100644 include/configs/ci20.h
> 
> I've looked into testing the remainder of this patchset, not seeing a
> newer version. You can find my branch here:
> 
> https://github.com/afaerber/u-boot/commits/ci20
> 
> In particular I fixed the MMC set_ios signature to silence a warning
> about the int vs. void return type, which I intend to clean up and submit.
> 
> The code compiled okay after some defconfig tweaks, save for a few
> unused-variable SPL-only warnings, but testing did not give any output.
> Investigating that, it seemed to me
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y was missing for
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR. Some other include options
> could be moved into defconfig, too.

Hm, so it broke again ? That's kinda sad ...

> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:
> 
>   LD  spl/u-boot-spl
> mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
> region `.sram'
> mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
> ../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
> make[2]: *** [spl/u-boot-spl] Error 1
> /home/andreas/OBS/u-boot/Makefile:1342: recipe for target
> 'spl/u-boot-spl' failed
> make[1]: *** [spl/u-boot-spl] Error 2
> make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
> Makefile:150: recipe for target 'sub-make' failed
> make: *** [sub-make] Error 2
> 
> I've reviewed all SPL Kconfig options and found three seemingly unneeded
> options defaulting to y, but I did not find a way to get this number
> down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
> even worse (~748).

The recommended one was gcc 6.x , again, when I submitted it, I had no
problem. So it seems U-Boot again gained bloat, oh well ...

> I also tried combining the downstream 4.8.1-built SPL
> with the upstream U-Boot (from without
> CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR), but still no output.
> 
> Is this the reason this series is not respun?

Eh ? No, the reason is I lack time :) The SPL will give you no output
though, since it is stripped down to bare minimum.

> Regards,
> Andreas
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2017-02-12 Thread Andreas Färber 
Hi Marek,

Am 01.12.2016 um 02:06 schrieb Marek Vasut:
> From: Paul Burton 
> 
> Add support for the Creator CI20 platform based on the JZ4780 SoC.
> The DTS file comes from Linux 4.6 as of revision
> 78800558d104e003f9ae92e0107f1de39cf9de9f
> 
> So far, there are still a few details which will have to be fixed
> once they are fleshed out in Linux:
> - pinmux: Thus far, this board just pokes the pinmux registers to
>   set the pinmux. For MMC in SPL, this will have to stay.
> But for full u-boot a proper pinmux driver will have to
> be added once the pinmux semantics in DT are in mainline
> Linux.
> - ethernet,efuse: DT bindings are missing from mainline Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  arch/mips/dts/Makefile|   1 +
>  arch/mips/dts/ci20.dts| 114 ++
>  arch/mips/mach-jz47xx/Kconfig |  11 ++
>  board/imgtec/ci20/Kconfig |  35 +
>  board/imgtec/ci20/Makefile|   5 +
>  board/imgtec/ci20/README  |  10 ++
>  board/imgtec/ci20/ci20.c  | 354 
> ++
>  configs/ci20_defconfig|  28 
>  include/configs/ci20.h| 105 +
>  9 files changed, 663 insertions(+)
>  create mode 100644 arch/mips/dts/ci20.dts
>  create mode 100644 board/imgtec/ci20/Kconfig
>  create mode 100644 board/imgtec/ci20/Makefile
>  create mode 100644 board/imgtec/ci20/README
>  create mode 100644 board/imgtec/ci20/ci20.c
>  create mode 100644 configs/ci20_defconfig
>  create mode 100644 include/configs/ci20.h

I've looked into testing the remainder of this patchset, not seeing a
newer version. You can find my branch here:

https://github.com/afaerber/u-boot/commits/ci20

In particular I fixed the MMC set_ios signature to silence a warning
about the int vs. void return type, which I intend to clean up and submit.

The code compiled okay after some defconfig tweaks, save for a few
unused-variable SPL-only warnings, but testing did not give any output.
Investigating that, it seemed to me
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y was missing for
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR. Some other include options
could be moved into defconfig, too.

CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y leads to this error:

  LD  spl/u-boot-spl
mipsel-suse-linux-ld.bfd: u-boot-spl section `.data' will not fit in
region `.sram'
mipsel-suse-linux-ld.bfd: region `.sram' overflowed by 288 bytes
../scripts/Makefile.spl:304: recipe for target 'spl/u-boot-spl' failed
make[2]: *** [spl/u-boot-spl] Error 1
/home/andreas/OBS/u-boot/Makefile:1342: recipe for target
'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 2
make[1]: Leaving directory '/home/andreas/OBS/u-boot/ci20'
Makefile:150: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2

I've reviewed all SPL Kconfig options and found three seemingly unneeded
options defaulting to y, but I did not find a way to get this number
down even a single byte with my GCC 6.3.1, and the recommended 4.8.1 was
even worse (~748). I also tried combining the downstream 4.8.1-built SPL
with the upstream U-Boot (from without
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR), but still no output.

Is this the reason this series is not respun?

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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[U-Boot] [PATCH 13/13] mips: jz47xx: Add Creator CI20 platform

2016-11-30 Thread Marek Vasut 
From: Paul Burton 

Add support for the Creator CI20 platform based on the JZ4780 SoC.
The DTS file comes from Linux 4.6 as of revision
78800558d104e003f9ae92e0107f1de39cf9de9f

So far, there are still a few details which will have to be fixed
once they are fleshed out in Linux:
- pinmux: Thus far, this board just pokes the pinmux registers to
  set the pinmux. For MMC in SPL, this will have to stay.
  But for full u-boot a proper pinmux driver will have to
  be added once the pinmux semantics in DT are in mainline
  Linux.
- ethernet,efuse: DT bindings are missing from mainline Linux.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 arch/mips/dts/Makefile|   1 +
 arch/mips/dts/ci20.dts| 114 ++
 arch/mips/mach-jz47xx/Kconfig |  11 ++
 board/imgtec/ci20/Kconfig |  35 +
 board/imgtec/ci20/Makefile|   5 +
 board/imgtec/ci20/README  |  10 ++
 board/imgtec/ci20/ci20.c  | 354 ++
 configs/ci20_defconfig|  28 
 include/configs/ci20.h| 105 +
 9 files changed, 663 insertions(+)
 create mode 100644 arch/mips/dts/ci20.dts
 create mode 100644 board/imgtec/ci20/Kconfig
 create mode 100644 board/imgtec/ci20/Makefile
 create mode 100644 board/imgtec/ci20/README
 create mode 100644 board/imgtec/ci20/ci20.c
 create mode 100644 configs/ci20_defconfig
 create mode 100644 include/configs/ci20.h

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 30fcc2b..e3473d9 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ci20.dts b/arch/mips/dts/ci20.dts
new file mode 100644
index 000..9dab5e6
--- /dev/null
+++ b/arch/mips/dts/ci20.dts
@@ -0,0 +1,114 @@
+/dts-v1/;
+
+#include "jz4780.dtsi"
+
+/ {
+   compatible = "img,ci20", "ingenic,jz4780";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x0 0x1000
+  0x3000 0x3000>;
+   };
+};
+
+ {
+   clock-frequency = <4800>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+
+   nandc: nand-controller@1 {
+   compatible = "ingenic,jz4780-nand";
+   reg = <1 0 0x100>;
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ingenic,bch-controller = <>;
+
+   ingenic,nemc-tAS = <10>;
+   ingenic,nemc-tAH = <5>;
+   ingenic,nemc-tBP = <10>;
+   ingenic,nemc-tAW = <15>;
+   ingenic,nemc-tSTRV = <100>;
+
+   nand@1 {
+   reg = <1>;
+
+   nand-ecc-step-size = <1024>;
+   nand-ecc-strength = <24>;
+   nand-ecc-mode = "hw";
+   nand-on-flash-bbt;
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   partition@0 {
+   label = "u-boot-spl";
+   reg = <0x0 0x0 0x0 0x80>;
+   };
+
+   partition@0x80 {
+   label = "u-boot";
+   reg = <0x0 0x80 0x0 0x20>;
+   };
+
+   partition@0xa0 {
+   label = "u-boot-env";
+   reg = <0x0 0xa0 0x0 0x20>;
+   };
+
+   partition@0xc0 {
+   label = "boot";
+   reg = <0x0 0xc0 0x0 0x400>;
+   };
+
+   partition@0x8c0 {
+   label = "system";
+   reg = <0x0 0x4c0 0x1 0xfb40>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+