Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
On Fri, 19 Dec 2014 18:05:49 +0100 Hans de Goede hdego...@redhat.com wrote: Hi, On 19-12-14 11:20, Siarhei Siamashka wrote: On Tue, 16 Dec 2014 21:31:38 +0100 Hans de Goede hdego...@redhat.com wrote: Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Can the commit message have more detailed information about the precise location of the original Allwinner code, which was used as the reference? No, it cannot because no code was referenced, I traced the boot0 binary to figure out what was needed to get dram going on the A23. Thanks for explaining. And good job extracting all the information from there. In this case, can we have a clear reference to this binary in the commit message? It might be useful to have a look at objdump logs when reviewing your patch. [...] +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c @@ -0,0 +1,340 @@ +/* + * Sun8i platform dram controller init. + * + * (C) Copyright 2014 Hans de Goede hdego...@redhat.com Is Allwinner copyright really not necessary here? + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. + */ You are well aware of this documentation since a long time ago, right? http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf I'm aware you've used various sources to figure out more about the A10 dram controller, since this DRAM controller seems significantly different I assumed your sources would not apply, it is good to hear that they do. I wonder how could you have ended up with this strange assumption? When I clearly told you that It looks like the Allwinner A31 DRAM controller registers are very similar to what is used in RK3288 and provided the links to the relevant sources and documentation back in September: http://lists.denx.de/pipermail/u-boot/2014-September/189199.html Then reminded yet again about this RK3288 similarity and used the mctl_phy-ptr0 register as an example: http://lists.denx.de/pipermail/u-boot/2014-December/198582.html When we were discussing the A31 DRAM controller, of course you should have expected the information about A31. Yes, A23 was not a part of the picture at that time. However comparing its registers with the information from spruhn7a.pdf and various Rockchip source code drops is a very natural thing to try. So far the best matching pairs (almost 100% identical PHY) are: Allwinner A10 (sun4i) - RK29xx Allwinner A31 (sun6i) - RK3288 Allwinner A23 (sun8i) - TI Keystone2 It's all the same family of DRAM controllers, very likely just different revisions/generations from the same supplier. I don't expect A80 or other Allwinner chips to be any different. [...] + else + writel(0x140b, mctl_phy-dcr); The bit 28 is marked as reserved and Reads return zeros in the TI Keystone2 documentation. It's a nice chance to test whether this write has any effect and whether it does modify the register. It modifies the register, so that means that at least that bit does not match the TI Keystone2 documentation. OK. -- Best regards, Siarhei Siamashka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
On Tue, 16 Dec 2014 21:31:38 +0100
Hans de Goede hdego...@redhat.com wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Can the commit message have more detailed information about the precise
location of the original Allwinner code, which was used as the
reference?
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/board.c | 3 +-
arch/arm/cpu/armv7/sunxi/dram_sun8i.c | 340
++
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
arch/arm/include/asm/arch-sunxi/dram_sun8i.h | 266
board/sunxi/Kconfig | 3 +-
configs/Ippo_q8h_v5_defconfig | 17 +-
include/configs/sun8i.h | 2 +
9 files changed, 631 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3e8975a..1e89937 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN4I)+= dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y+= start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3e80c..bc98c56 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,7 +114,8 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if defined CONFIG_SPL_BUILD defined CONFIG_MACH_SUN6I
+#if defined CONFIG_SPL_BUILD \
+ (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
new file mode 100644
index 000..3736fd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -0,0 +1,340 @@
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
Is Allwinner copyright really not necessary here?
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ */
You are well aware of this documentation since a long time ago, right?
http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
Please open it and find Table4-2 DDR3 PHY Registers. Then have a
look at the sunxi_mctl_phy_reg struct from your patch. Compare
the register names and their offsets. Looks like we are reasonably
lucky again.
Just as an example, I have commented about a few hardware registers
at different locations in the code.
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x3,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 100 / 2, 1, 2,
+dram_para.tpr13 0x4);
Is it really necessary to have the PLL5 setup so complicated and full
of magic?
+
+ /* deassert ahb mctl reset */
+ setbits_le32(ccm-ahb_reset0_cfg, 1 AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb
Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
Hi, On 18-12-14 20:17, Ian Campbell wrote: On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote: Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede hdego...@redhat.com +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. On that basis I've only really given this a quick glance. I've no problem with it. Couple of queries about the defconfig changes: diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index 50c2f93..37aa46d 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -1,8 +1,15 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5 -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I=y -CONFIG_TARGET_IPPO_Q8H_V5=y Not replaced with a S: variant? I know you want CONFIG_TARGET to go, but I don't think that was part of what you intended in this patch. Right, I'll add that back. -CONFIG_DEFAULT_DEVICE_TREE=sun8i-a23-ippo-q8h-v5.dtb +CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v5.dtb The switch from CONFIG_DEFAULT_DEVICE_TREE to CONFIG_FDTFILE conversion seems a little out of place too. That was deliberate, the CONFIG_DEFAULT_DEVICE_TREE is the wrong CONFIG define to use to set the dtb for the kernel. I'll split the Ippo_q8h_v5_defconfig changes out into a separate patch and mention this in the commit message. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
Hi,
On 19-12-14 11:20, Siarhei Siamashka wrote:
On Tue, 16 Dec 2014 21:31:38 +0100
Hans de Goede hdego...@redhat.com wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Can the commit message have more detailed information about the precise
location of the original Allwinner code, which was used as the
reference?
No, it cannot because no code was referenced, I traced the boot0 binary to
figure out what was needed to get dram going on the A23.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/board.c | 3 +-
arch/arm/cpu/armv7/sunxi/dram_sun8i.c | 340 ++
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
arch/arm/include/asm/arch-sunxi/dram_sun8i.h | 266
board/sunxi/Kconfig | 3 +-
configs/Ippo_q8h_v5_defconfig | 17 +-
include/configs/sun8i.h | 2 +
9 files changed, 631 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3e8975a..1e89937 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3e80c..bc98c56 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,7 +114,8 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if defined CONFIG_SPL_BUILD defined CONFIG_MACH_SUN6I
+#if defined CONFIG_SPL_BUILD \
+ (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
new file mode 100644
index 000..3736fd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -0,0 +1,340 @@
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
Is Allwinner copyright really not necessary here?
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ */
You are well aware of this documentation since a long time ago, right?
http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
I'm aware you've used various sources to figure out more about the A10
dram controller, since this DRAM controller seems significantly different
I assumed your sources would not apply, it is good to hear that they do.
I'll add a comment to the next version of this patch referencing that
document.
Please open it and find Table4-2 DDR3 PHY Registers. Then have a
look at the sunxi_mctl_phy_reg struct from your patch. Compare
the register names and their offsets. Looks like we are reasonably
lucky again.
Just as an example, I have commented about a few hardware registers
at different locations in the code.
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x3,
+};
+
+static void mctl_sys_init(void)
+{
+
Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede hdego...@redhat.com wrote:
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/board.c | 3 +-
arch/arm/cpu/armv7/sunxi/dram_sun8i.c | 340
++
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
arch/arm/include/asm/arch-sunxi/dram_sun8i.h | 266
board/sunxi/Kconfig | 3 +-
configs/Ippo_q8h_v5_defconfig | 17 +-
include/configs/sun8i.h | 2 +
9 files changed, 631 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3e8975a..1e89937 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3e80c..bc98c56 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,7 +114,8 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if defined CONFIG_SPL_BUILD defined CONFIG_MACH_SUN6I
+#if defined CONFIG_SPL_BUILD \
+ (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
new file mode 100644
index 000..3736fd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -0,0 +1,340 @@
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ */
+
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x3,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 100 / 2, 1, 2,
+ dram_para.tpr13 0x4);
+
+ /* deassert ahb mctl reset */
+ setbits_le32(ccm-ahb_reset0_cfg, 1 AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb mctl clock */
+ setbits_le32(ccm-ahb_gate0, 1 AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_apply_odt_correction(u32 *reg, int correction)
+{
+ int val;
+
+ val = (readl(reg) 8) 0xff;
+ val += correction;
+
+ /* clamp */
+ if (val 0)
+ val = 0;
+ else if (val 255)
+ val = 255;
+
+ clrsetbits_le32(reg, 0xff00, val 8);
+}
+
+static void mctl_init(u32 *bus_width)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+
Re: [U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
On Tue, 2014-12-16 at 21:31 +0100, Hans de Goede wrote: Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede hdego...@redhat.com +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. On that basis I've only really given this a quick glance. I've no problem with it. Couple of queries about the defconfig changes: diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index 50c2f93..37aa46d 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -1,8 +1,15 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS=CONS_INDEX=5 -CONFIG_ARM=y -CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I=y -CONFIG_TARGET_IPPO_Q8H_V5=y Not replaced with a S: variant? I know you want CONFIG_TARGET to go, but I don't think that was part of what you intended in this patch. -CONFIG_DEFAULT_DEVICE_TREE=sun8i-a23-ippo-q8h-v5.dtb +CONFIG_FDTFILE=sun8i-a23-ippo-q8h-v5.dtb The switch from CONFIG_DEFAULT_DEVICE_TREE to CONFIG_FDTFILE conversion seems a little out of place too. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 13/14] sun8i: Add dram initialization support
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/board.c | 3 +-
arch/arm/cpu/armv7/sunxi/dram_sun8i.c | 340 ++
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
arch/arm/include/asm/arch-sunxi/dram_sun8i.h | 266
board/sunxi/Kconfig | 3 +-
configs/Ippo_q8h_v5_defconfig | 17 +-
include/configs/sun8i.h | 2 +
9 files changed, 631 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3e8975a..1e89937 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3e80c..bc98c56 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,7 +114,8 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
-#if defined CONFIG_SPL_BUILD defined CONFIG_MACH_SUN6I
+#if defined CONFIG_SPL_BUILD \
+ (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
new file mode 100644
index 000..3736fd1
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -0,0 +1,340 @@
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ */
+
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x3,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 100 / 2, 1, 2,
+ dram_para.tpr13 0x4);
+
+ /* deassert ahb mctl reset */
+ setbits_le32(ccm-ahb_reset0_cfg, 1 AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb mctl clock */
+ setbits_le32(ccm-ahb_gate0, 1 AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_apply_odt_correction(u32 *reg, int correction)
+{
+ int val;
+
+ val = (readl(reg) 8) 0xff;
+ val += correction;
+
+ /* clamp */
+ if (val 0)
+ val = 0;
+ else if (val 255)
+ val = 255;
+
+ clrsetbits_le32(reg, 0xff00, val 8);
+}
+
+static void mctl_init(u32 *bus_width)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const
