Re: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-29 Thread Mugunthan V N 
On Monday 25 July 2016 03:45 PM, Vignesh R wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
> 
> Signed-off-by: Vignesh R 

Reviewed-by: Mugunthan V N 

Regards
Mugunthan V N

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Re: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-28 Thread Jagan Teki 
On 27 July 2016 at 17:40, Vignesh R  wrote:
>
>
> On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
>> On 25 July 2016 at 15:45, Vignesh R  wrote:
>>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>>> the driver to use the same.
>>>
>>> Signed-off-by: Vignesh R 
>>> ---
>>>  drivers/spi/ti_qspi.c | 17 -
>>>  1 file changed, 12 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>>> index fa7ee229878a..bb72cb03ec24 100644
>>> --- a/drivers/spi/ti_qspi.c
>>> +++ b/drivers/spi/ti_qspi.c
>>> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>>>
>>>  /* ti qpsi register bit masks */
>>>  #define QSPI_TIMEOUT200
>>> -#define QSPI_FCLK   19200
>>> +#define QSPI_FCLK  19200
>>> +#define QSPI_DRA7XX_FCLK7680
>>>  /* clock control */
>>>  #define QSPI_CLK_EN BIT(31)
>>>  #define QSPI_CLK_DIV_MAX0x
>>> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>>>  #endif
>>> struct ti_qspi_regs *base;
>>> void *ctrl_mod_mmap;
>>> +   ulong fclk;
>>> unsigned int mode;
>>> u32 cmd;
>>> u32 dc;
>>> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
>>> uint hz)
>>> if (!hz)
>>> clk_div = 0;
>>> else
>>> -   clk_div = (QSPI_FCLK / hz) - 1;
>>> +   clk_div = (priv->fclk / hz) - 1;
>>
>> Then how this relate to max_hz (priv->max_hz), look like it is not
>> using anywhere.
>
> I think priv-max_hz defines the max frequency QSPI IP can support (flash
> node can always be configured to run at higher or lower frequency which
> is specified by spi-max-frequency in flash subnode). What's missing is a
> check to see if frequency requested in set_speed() is not greater than
> priv->max_hz. I will implement that in another series.

Reviewed-by: Jagan Teki 

-- 
Jagan.
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Re: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-27 Thread Vignesh R 


On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
> On 25 July 2016 at 15:45, Vignesh R  wrote:
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>> the driver to use the same.
>>
>> Signed-off-by: Vignesh R 
>> ---
>>  drivers/spi/ti_qspi.c | 17 -
>>  1 file changed, 12 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> index fa7ee229878a..bb72cb03ec24 100644
>> --- a/drivers/spi/ti_qspi.c
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>>
>>  /* ti qpsi register bit masks */
>>  #define QSPI_TIMEOUT200
>> -#define QSPI_FCLK   19200
>> +#define QSPI_FCLK  19200
>> +#define QSPI_DRA7XX_FCLK7680
>>  /* clock control */
>>  #define QSPI_CLK_EN BIT(31)
>>  #define QSPI_CLK_DIV_MAX0x
>> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>>  #endif
>> struct ti_qspi_regs *base;
>> void *ctrl_mod_mmap;
>> +   ulong fclk;
>> unsigned int mode;
>> u32 cmd;
>> u32 dc;
>> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
>> uint hz)
>> if (!hz)
>> clk_div = 0;
>> else
>> -   clk_div = (QSPI_FCLK / hz) - 1;
>> +   clk_div = (priv->fclk / hz) - 1;
> 
> Then how this relate to max_hz (priv->max_hz), look like it is not
> using anywhere.

I think priv-max_hz defines the max frequency QSPI IP can support (flash
node can always be configured to run at higher or lower frequency which
is specified by spi-max-frequency in flash subnode). What's missing is a
check to see if frequency requested in set_speed() is not greater than
priv->max_hz. I will implement that in another series.


-- 
Regards
Vignesh
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Re: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-27 Thread Jagan Teki 
On 25 July 2016 at 15:45, Vignesh R  wrote:
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
>
> Signed-off-by: Vignesh R 
> ---
>  drivers/spi/ti_qspi.c | 17 -
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index fa7ee229878a..bb72cb03ec24 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  /* ti qpsi register bit masks */
>  #define QSPI_TIMEOUT200
> -#define QSPI_FCLK   19200
> +#define QSPI_FCLK  19200
> +#define QSPI_DRA7XX_FCLK7680
>  /* clock control */
>  #define QSPI_CLK_EN BIT(31)
>  #define QSPI_CLK_DIV_MAX0x
> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>  #endif
> struct ti_qspi_regs *base;
> void *ctrl_mod_mmap;
> +   ulong fclk;
> unsigned int mode;
> u32 cmd;
> u32 dc;
> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
> uint hz)
> if (!hz)
> clk_div = 0;
> else
> -   clk_div = (QSPI_FCLK / hz) - 1;
> +   clk_div = (priv->fclk / hz) - 1;

Then how this relate to max_hz (priv->max_hz), look like it is not
using anywhere.

-- 
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Re: [U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-25 Thread Tom Rini 
On Mon, Jul 25, 2016 at 03:45:45PM +0530, Vignesh R wrote:

> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
> the driver to use the same.
> 
> Signed-off-by: Vignesh R 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

2016-07-25 Thread Vignesh R 
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R 
---
 drivers/spi/ti_qspi.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index fa7ee229878a..bb72cb03ec24 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT200
-#define QSPI_FCLK   19200
+#define QSPI_FCLK  19200
+#define QSPI_DRA7XX_FCLK7680
 /* clock control */
 #define QSPI_CLK_EN BIT(31)
 #define QSPI_CLK_DIV_MAX0x
@@ -101,6 +102,7 @@ struct ti_qspi_priv {
 #endif
struct ti_qspi_regs *base;
void *ctrl_mod_mmap;
+   ulong fclk;
unsigned int mode;
u32 cmd;
u32 dc;
@@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
uint hz)
if (!hz)
clk_div = 0;
else
-   clk_div = (QSPI_FCLK / hz) - 1;
+   clk_div = (priv->fclk / hz) - 1;
 
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
@@ -366,8 +368,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+   priv->fclk = QSPI_DRA7XX_FCLK;
 #else
priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+   priv->fclk = QSPI_FCLK;
 #endif
 
ti_spi_set_speed(priv, max_hz);
@@ -520,7 +524,10 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int 
bitlen,
 
 static int ti_qspi_probe(struct udevice *bus)
 {
-   /* Nothing to do in probe */
+   struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+   priv->fclk = dev_get_driver_data(bus);
+
return 0;
 }
 
@@ -572,8 +579,8 @@ static const struct dm_spi_ops ti_qspi_ops = {
 };
 
 static const struct udevice_id ti_qspi_ids[] = {
-   { .compatible = "ti,dra7xxx-qspi" },
-   { .compatible = "ti,am4372-qspi" },
+   { .compatible = "ti,dra7xxx-qspi",  .data = QSPI_DRA7XX_FCLK},
+   { .compatible = "ti,am4372-qspi",   .data = QSPI_FCLK},
{ }
 };
 
-- 
2.9.2

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