On 11/05/2012 05:00 PM, Simon Glass wrote:
Hi Stephen,
On Mon, Nov 5, 2012 at 3:04 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot
Hi Stephen,
On Tue, Nov 6, 2012 at 10:50 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/05/2012 05:00 PM, Simon Glass wrote:
Hi Stephen,
On Mon, Nov 5, 2012 at 3:04 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Tegra's MMC driver does DMA,
From: Stephen Warren swar...@nvidia.com
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note:
Hi Stephen,
On Mon, Nov 5, 2012 at 3:04 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To
4 matches
Mail list logo