From: "Ye.Li" <b37...@freescale.com>
Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <b37...@freescale.com>
Signed-off-by: Peng Fan <peng....@freescale.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 29de624..e3474e7 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -645,6 +645,9 @@ void v7_outer_cache_enable(void)
#ifndef CONFIG_MX6Q
val |= 0x40800000;
+#else
+ if (is_mx6dqp())
+ val |= 0x40800000;
#endif
writel(val, &pl310->pl310_prefetch_ctrl);
--
1.8.4
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