Re: [U-Boot] [PATCH 4/4] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
On 5.6.2018 09:21, Siva Durga Prasad Paladugu wrote:
> Add configuration files/dtses for mini u-boot configuration
> which runs on smaller footprint OCM memory. This configuration
> only has required parallel nor flash support.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/zynq-cse-nor.dts | 88
> ++
> configs/zynq_cse_nor_defconfig | 50
> 3 files changed, 139 insertions(+)
> create mode 100644 arch/arm/dts/zynq-cse-nor.dts
> create mode 100644 configs/zynq_cse_nor_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 71b7c3a..9e29fe6 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
> dtb-$(CONFIG_ARCH_ZYNQ) += \
> zynq-cc108.dtb \
> zynq-cse-nand.dtb \
> + zynq-cse-nor.dtb \
> zynq-cse-qspi-single.dtb \
> zynq-microzed.dtb \
> zynq-picozed.dtb \
> diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
> new file mode 100644
> index 000..ba6f9a1
> --- /dev/null
> +++ b/arch/arm/dts/zynq-cse-nor.dts
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Xilinx CSE NOR board DTS
> + *
> + * Copyright (C) 2018 Xilinx, Inc.
> + */
> +/dts-v1/;
> +#include "zynq-7000.dtsi"
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Zynq CSE NOR Board";
> + compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
> +
> + aliases {
> + serial0 =
> + };
> +
> + memory@fffc {
> + device_type = "memory";
> + reg = <0xFFFC 0x4>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + dcc: dcc {
> + compatible = "arm,dcc";
> + status = "disabled";
> + u-boot,dm-pre-reloc;
> + };
> +
> + amba: amba {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <>;
> + ranges;
> +
> + intc: interrupt-controller@f8f01000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0xF8F01000 0x1000>,
> + <0xF8F00100 0x100>;
> + };
> +
> + slcr: slcr@f800 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
> + reg = <0xF800 0x1000>;
> + ranges;
> + clkc: clkc@100 {
> + #clock-cells = <1>;
> + compatible = "xlnx,ps7-clkc";
> + fclk-enable = <0xf>;
> + clock-output-names = "armpll", "ddrpll",
> + "iopll", "cpu_6or4x",
> + "cpu_3or2x", "cpu_2x", "cpu_1x",
> + "ddr2x", "ddr3x", "dci",
> + "lqspi", "smc", "pcap", "gem0",
> + "gem1", "fclk0", "fclk1",
> + "fclk2", "fclk3", "can0",
> + "can1", "sdio0", "sdio1",
> + "uart0", "uart1", "spi0",
> + "spi1", "dma", "usb0_aper",
> + "usb1_aper", "gem0_aper",
> + "gem1_aper", "sdio0_aper",
> + "sdio1_aper", "spi0_aper",
> + "spi1_aper", "can0_aper",
> + "can1_aper", "i2c0_aper",
> + "i2c1_aper", "uart0_aper",
> + "uart1_aper", "gpio_aper",
> + "lqspi_aper", "smc_aper",
> + "swdt", "dbg_trc", "dbg_apb";
> + reg = <0x100 0x100>;
> + };
> + };
> + };
> +
> +};
> +
> + {
> + status = "okay";
> +};
> diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
> new file mode 100644
> index 000..842d520
> --- /dev/null
> +++ b/configs/zynq_cse_nor_defconfig
> @@ -0,0 +1,50 @@
> +CONFIG_ARM=y
> +CONFIG_SYS_CONFIG_NAME="zynq_cse"
> +CONFIG_ARCH_ZYNQ=y
> +CONFIG_SYS_TEXT_BASE=0xFFFC
> +CONFIG_SPL_STACK_R_ADDR=0x20
> +CONFIG_SYS_MALLOC_LEN=0x1000
>
[U-Boot] [PATCH 4/4] arm: zynq: Add parallel NOR flash mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configuration
which runs on smaller footprint OCM memory. This configuration
only has required parallel nor flash support.
Signed-off-by: Siva Durga Prasad Paladugu
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-cse-nor.dts | 88 ++
configs/zynq_cse_nor_defconfig | 50
3 files changed, 139 insertions(+)
create mode 100644 arch/arm/dts/zynq-cse-nor.dts
create mode 100644 configs/zynq_cse_nor_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 71b7c3a..9e29fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 000..ba6f9a1
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 =
+ };
+
+ memory@fffc {
+ device_type = "memory";
+ reg = <0xFFFC 0x4>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF800 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+ {
+ status = "okay";
+};
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
new file mode 100644
index 000..842d520
--- /dev/null
+++ b/configs/zynq_cse_nor_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0xFFFC
+CONFIG_SPL_STACK_R_ADDR=0x20
+CONFIG_SYS_MALLOC_LEN=0x1000
+CONFIG_ZYNQ_M29EW_WB_HACK=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-nor"
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_PROMPT="Zynq>
