Re: [U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node

2019-06-05 Thread Rick Chen 
Hi Bin

Bin Meng  於 2019年6月4日 週二 上午10:48寫道：
>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes  wrote:
> >
> > From: Rick Chen 
> >
> > When L2 node exists inside cpus node, uclass_get_device
> > can not parse L2 node successfully. So move it outside
> > from cpus node.
> >
> > Also add tag-ram-ctl and data-ram-ctl attributes for
> > v5l2 cache controller driver. This can adjust timing
> > by requirement from dtb to improve performance.
> >
> > Signed-off-by: Rick Chen 
> > Cc: Greentime Hu 
> > ---
> >  arch/riscv/dts/ae350_32.dts | 17 +++--
> >  arch/riscv/dts/ae350_64.dts | 17 +++--
> >  2 files changed, 22 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > index cb6ee13..83abfcb 100644
> > --- a/arch/riscv/dts/ae350_32.dts
> > +++ b/arch/riscv/dts/ae350_32.dts
> > @@ -62,13 +62,18 @@
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > +   };
> >
> > -   L2: l2-cache@e050 {
> > -   compatible = "cache";
> > -   cache-level = <2>;
> > -   cache-size = <0x4>;
> > -   reg = <0x0 0xe050 0x0 0x4>;
> > -   };
> > +   L2: l2-cache@e050 {
> > +   compatible = "cache";
>
> too generic compatible string (see my previous comments in patch [1/6])

Same replying  in patch [1/6]
>
> > +   cache-level = <2>;
> > +   cache-size = <0x4>;
> > +   reg = <0xe050 0x4>;
> > +   andes,inst-prefetch = <3>;
> > +   andes,data-prefetch = <3>;
> > +   // The value format is 
>
> nits: no //, use /* */

OK
I will use /* */ instead of //

>
> > +   andes,tag-ram-ctl = <0 0>;
> > +   andes,data-ram-ctl = <0 0>;
> > };
> >
> > memory@0 {
> > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> > index 705491a..7009bdc 100644
> > --- a/arch/riscv/dts/ae350_64.dts
> > +++ b/arch/riscv/dts/ae350_64.dts
> > @@ -62,13 +62,18 @@
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > +   };
> >
> > -   L2: l2-cache@e050 {
> > -   compatible = "cache";
> > -   cache-level = <2>;
> > -   cache-size = <0x4>;
> > -   reg = <0x0 0xe050 0x0 0x4>;
> > -   };
> > +   L2: l2-cache@e050 {
> > +   compatible = "cache";
> > +   cache-level = <2>;
> > +   cache-size = <0x4>;
> > +   reg = <0x0 0xe050 0x0 0x4>;
> > +   andes,inst-prefetch = <3>;
> > +   andes,data-prefetch = <3>;
> > +   // The value format is 
>
> nits: no //, use /* */

I will use /* */ instead of //

Thanks
Rick

>
> > +   andes,tag-ram-ctl = <0 0>;
> > +   andes,data-ram-ctl = <0 0>;
> > };
> >
> > memory@0 {
> > --
>
> Regards,
> Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node

2019-06-03 Thread Bin Meng 
Hi Rick,

On Tue, May 28, 2019 at 5:44 PM Andes  wrote:
>
> From: Rick Chen 
>
> When L2 node exists inside cpus node, uclass_get_device
> can not parse L2 node successfully. So move it outside
> from cpus node.
>
> Also add tag-ram-ctl and data-ram-ctl attributes for
> v5l2 cache controller driver. This can adjust timing
> by requirement from dtb to improve performance.
>
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> ---
>  arch/riscv/dts/ae350_32.dts | 17 +++--
>  arch/riscv/dts/ae350_64.dts | 17 +++--
>  2 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> index cb6ee13..83abfcb 100644
> --- a/arch/riscv/dts/ae350_32.dts
> +++ b/arch/riscv/dts/ae350_32.dts
> @@ -62,13 +62,18 @@
> compatible = "riscv,cpu-intc";
> };
> };
> +   };
>
> -   L2: l2-cache@e050 {
> -   compatible = "cache";
> -   cache-level = <2>;
> -   cache-size = <0x4>;
> -   reg = <0x0 0xe050 0x0 0x4>;
> -   };
> +   L2: l2-cache@e050 {
> +   compatible = "cache";

too generic compatible string (see my previous comments in patch [1/6])

> +   cache-level = <2>;
> +   cache-size = <0x4>;
> +   reg = <0xe050 0x4>;
> +   andes,inst-prefetch = <3>;
> +   andes,data-prefetch = <3>;
> +   // The value format is 

nits: no //, use /* */

> +   andes,tag-ram-ctl = <0 0>;
> +   andes,data-ram-ctl = <0 0>;
> };
>
> memory@0 {
> diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> index 705491a..7009bdc 100644
> --- a/arch/riscv/dts/ae350_64.dts
> +++ b/arch/riscv/dts/ae350_64.dts
> @@ -62,13 +62,18 @@
> compatible = "riscv,cpu-intc";
> };
> };
> +   };
>
> -   L2: l2-cache@e050 {
> -   compatible = "cache";
> -   cache-level = <2>;
> -   cache-size = <0x4>;
> -   reg = <0x0 0xe050 0x0 0x4>;
> -   };
> +   L2: l2-cache@e050 {
> +   compatible = "cache";
> +   cache-level = <2>;
> +   cache-size = <0x4>;
> +   reg = <0x0 0xe050 0x0 0x4>;
> +   andes,inst-prefetch = <3>;
> +   andes,data-prefetch = <3>;
> +   // The value format is 

nits: no //, use /* */

> +   andes,tag-ram-ctl = <0 0>;
> +   andes,data-ram-ctl = <0 0>;
> };
>
> memory@0 {
> --

Regards,
Bin
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node

2019-05-28 Thread Andes 
From: Rick Chen 

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/dts/ae350_32.dts | 17 +++--
 arch/riscv/dts/ae350_64.dts | 17 +++--
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..83abfcb 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0xe050 0x4>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   // The value format is 
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..7009bdc 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   // The value format is 
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot