Re: [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

Hi Bin Bin Meng 於 2019年3月20日 週三 下午3:22寫道： > > Hi Rick, > > On Tue, Mar 19, 2019 at 5:12 PM Andes wrote: > > > > From: Rick Chen > > > > nits: remove the ending period in the commit title OK I will remove it. Thanks for review. Rick > > > Limit the cache configuration only can be supported

Re: [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

Hi Rick, On Tue, Mar 19, 2019 at 5:12 PM Andes wrote: > > From: Rick Chen > nits: remove the ending period in the commit title > Limit the cache configuration only can be supported in M mode. > It can not be manipulated in S mode. > > Signed-off-by: Rick Chen > Cc: Greentime Hu > --- >

[U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

From: Rick Chen Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig