Re: [U-Boot] [PATCH v2] ARM: am335x: Add phyCORE AM335x R2 support
Hi All, Thank you Marek for the feedback. I addressed all of your concerns, the most important of is mentioned below: On 4/25/19 12:52 PM, Marek Vasut wrote: The Linux commit from which the DTs came is missing. Added Keep the list sorted alphabetically please. (PHY... is below PCM...) Fixed. Sorry, that was as howler. Just curious , was there ever AM335x_R1 ? Why do we use the _R2 suffix here ?> The AM335x (without the R2) was the Phytec pcm051. So I stuck with adding R2 to distinguish the two. (I don't have a pcm051, so I did not want to mess with it.) +#ifndef CONFIG_DM_I2C CONFIG_IS_ENABLED(DM_I2C) This one is causing some headaches. I can't find any references to CONFIG_SPL_DM_I2C, even though we actually use DM for I2C in the SPL, so that change causes things to break a bit. As an improvement, I changed the code to use #if defined(CONFIG_DM_I2C) instead of #ifndef. We could always simply drop the Non-DM support instead, I guess? On 4/25/19 12:43 PM, Marek Vasut wrote:> Take a look at > configs/am335x_evm_defconfig:CONFIG_DM_USB_GADGET=y > > Maybe we can at least get rid of some of the hard-coded USB non-DM > stuff. I simply removed the hard-coded USB stuff, as the DM_USB was already enabled and working anyways. DM_USB_GADGET was also enabled. Thanks for the recommendation. Best regards, Niel Fourie -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-21 Fax: +49-8142-66989-80 Email: lu...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] ARM: am335x: Add phyCORE AM335x R2 support
On 4/25/19 10:32 AM, Niel Fourie wrote:
> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> phyBOARD-Wega AM335x.
>
> CPU : AM335X-GP rev 2.1
> Model: Phytec AM335x phyBOARD-WEGA
> DRAM: 256 MiB
> NAND: 256 MiB
> MMC: OMAP SD/MMC: 0
> eth0: ethernet@4a10
>
> Working:
> - Eth0
> - i2C
> - MMC/SD
> - NAND
> - UART
> - USB (host)
The Linux commit from which the DTs came is missing.
[...]
> diff --git a/arch/arm/mach-omap2/am33xx/Kconfig
> b/arch/arm/mach-omap2/am33xx/Kconfig
> index 500df1aa11..d6b0ea2246 100644
> --- a/arch/arm/mach-omap2/am33xx/Kconfig
> +++ b/arch/arm/mach-omap2/am33xx/Kconfig
> @@ -156,6 +156,13 @@ config TARGET_ETAMIN
> select DM_SERIAL
> imply CMD_DM
>
> +config TARGET_PHYCORE_AM335X_R2
> + bool "Support phyCORE AM335X R2"
> + select DM
> + select DM_GPIO
> + select DM_SERIAL
> + imply CMD_DM
> +
Keep the list sorted alphabetically please. (PHY... is below PCM...)
> config TARGET_PCM051
> bool "Support pcm051"
> select DM
> diff --git a/board/phytec/phycore_am335x_r2/Kconfig
> b/board/phytec/phycore_am335x_r2/Kconfig
> new file mode 100644
> index 00..77055e043c
> --- /dev/null
> +++ b/board/phytec/phycore_am335x_r2/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_PHYCORE_AM335X_R2
Just curious , was there ever AM335x_R1 ? Why do we use the _R2 suffix
here ?
[...]
> diff --git a/board/phytec/phycore_am335x_r2/board.c
> b/board/phytec/phycore_am335x_r2/board.c
> new file mode 100644
> index 00..ece9edcfbd
> --- /dev/null
> +++ b/board/phytec/phycore_am335x_r2/board.c
> @@ -0,0 +1,262 @@
[...]
> +void sdram_init(void)
> +{
> + int ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
> +
> + if (fdtdec_setup_mem_size_base())
> + gd->ram_size = SZ_256M;
Nice
> + switch (gd->ram_size) {
> + case SZ_1G:
> + ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
> + break;
> + case SZ_512M:
> + ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
> + break;
> + case SZ_256M:
> + default:
> + ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
Add a missing "break;" here for completeness.
> + }
> +
> + config_ddr(DDR_CLK_MHZ, ,
> +_timings[ram_type_index].ddr3_data,
> +_cmd_ctrl_data,
> +_timings[ram_type_index].ddr3_emif_reg_data, 0);
> +}
> +
> +const struct dpll_params *get_dpll_mpu_params(void)
> +{
> + int ind = get_sys_clk_index();
> + int freq = am335x_get_efuse_mpu_max_freq(cdev);
> +
> + switch (freq) {
> + case MPUPLL_M_1000:
> + return _mpu_opp[ind][5];
> + case MPUPLL_M_800:
> + return _mpu_opp[ind][4];
> + case MPUPLL_M_720:
> + return _mpu_opp[ind][3];
> + case MPUPLL_M_600:
> + return _mpu_opp[ind][2];
> + case MPUPLL_M_500:
> + return _mpu_opp100;
> + case MPUPLL_M_300:
> + return _mpu_opp[ind][0];
> + }
> +
> + return _mpu_opp[ind][0];
> +}
> +
> +void scale_vcores_generic(int freq)
> +{
> + int sil_rev, mpu_vdd;
> +
> + /*
> + * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
> + * CORE voltage of 1.10V. For MPU voltage we need to switch based on
> + * the frequency we are running at.
> + */
> +#ifndef CONFIG_DM_I2C
CONFIG_IS_ENABLED(DM_I2C)
> + if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
> + return;
> +#else
> + if (power_tps65910_init(0))
> + return;
> +#endif
> + /*
> + * Depending on MPU clock and PG we will need a different
> + * VDD to drive at that speed.
> + */
> + sil_rev = readl(>deviceid) >> 28;
> + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
> +
> + /* Tell the TPS65910 to use i2c */
> + tps65910_set_i2c_control();
> +
> + /* First update MPU voltage. */
> + if (tps65910_voltage_update(MPU, mpu_vdd))
> + return;
> +
> + /* Second, update the CORE voltage. */
> + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
> + return;
> +}
[...]
> diff --git a/include/configs/phycore_am335x_r2.h
> b/include/configs/phycore_am335x_r2.h
> new file mode 100644
> index 00..a512de8838
> --- /dev/null
> +++ b/include/configs/phycore_am335x_r2.h
> @@ -0,0 +1,138 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * phycore_am335x_r2.h
> + *
> + * Phytec phyCORE-AM335x R2 (pcl060) boards information header
> + *
> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +#ifndef __CONFIG_PHYCORE_AM335x_R2_H
> +#define __CONFIG_PHYCORE_AM335x_R2_H
> +
> +#include
> +
> +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Use SZ_128K macro
> +#define
[U-Boot] [PATCH v2] ARM: am335x: Add phyCORE AM335x R2 support
Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.
CPU : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0
eth0: ethernet@4a10
Working:
- Eth0
- i2C
- MMC/SD
- NAND
- UART
- USB (host)
Signed-off-by: Niel Fourie
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/am335x-phycore-som.dtsi | 322 +
arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 40 +++
arch/arm/dts/am335x-wega-rdk.dts | 23 ++
arch/arm/dts/am335x-wega.dtsi | 230 +++
arch/arm/mach-omap2/Kconfig| 1 +
arch/arm/mach-omap2/am33xx/Kconfig | 7 +
board/phytec/phycore_am335x_r2/Kconfig | 15 +
board/phytec/phycore_am335x_r2/MAINTAINERS | 7 +
board/phytec/phycore_am335x_r2/Makefile| 11 +
board/phytec/phycore_am335x_r2/board.c | 262 +
board/phytec/phycore_am335x_r2/board.h | 24 ++
board/phytec/phycore_am335x_r2/mux.c | 117
configs/phycore-am335x-r2-wega_defconfig | 79 +
include/configs/phycore_am335x_r2.h| 138 +
15 files changed, 1278 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-phycore-som.dtsi
create mode 100644 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
create mode 100644 arch/arm/dts/am335x-wega-rdk.dts
create mode 100644 arch/arm/dts/am335x-wega.dtsi
create mode 100644 board/phytec/phycore_am335x_r2/Kconfig
create mode 100644 board/phytec/phycore_am335x_r2/MAINTAINERS
create mode 100644 board/phytec/phycore_am335x_r2/Makefile
create mode 100644 board/phytec/phycore_am335x_r2/board.c
create mode 100644 board/phytec/phycore_am335x_r2/board.h
create mode 100644 board/phytec/phycore_am335x_r2/mux.c
create mode 100644 configs/phycore-am335x-r2-wega_defconfig
create mode 100644 include/configs/phycore_am335x_r2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5fe998914a..0a876997ed 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -253,7 +253,8 @@ dtb-$(CONFIG_AM33XX) += \
am335x-chiliboard.dtb \
am335x-sl50.dtb \
am335x-base0033.dtb \
- am335x-guardian.dtb
+ am335x-guardian.dtb \
+ am335x-wega-rdk.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb\
am43x-epos-evm.dtb \
am437x-idk-evm.dtb \
diff --git a/arch/arm/dts/am335x-phycore-som.dtsi
b/arch/arm/dts/am335x-phycore-som.dtsi
new file mode 100644
index 00..8d7c19e5e1
--- /dev/null
+++ b/arch/arm/dts/am335x-phycore-som.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include
+
+/ {
+ model = "Phytec AM335x phyCORE";
+ compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+ aliases {
+ rtc0 = _rtc;
+ rtc1 =
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <_reg>;
+ };
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x1000>; /* 256 MB */
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ vcc5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+};
+
+/* Crypto Module */
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* Ethernet */
+_pinmux {
+ ethernet0_pins: pinmux_ethernet0 {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)
/* mii1_crs.rmii1_crs_dv */
+ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)
/* mii1_rxerr.rmii1_rxerr */
+ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)
/* mii1_txen.rmii1_txen */
+ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)
/* mii1_txd1.rmii1_txd1 */
+ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)
/* mii1_txd0.rmii1_txd0 */
+ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)
/* mii1_rxd1.rmii1_rxd1 */
+ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)
/* mii1_rxd0.rmii1_rxd0 */
+ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* rmii1_refclk.rmii1_refclk */
+ >;
+
