Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/20/2017 03:07 PM, Dalon Westergreen wrote:
[...]
>>> Okay, after much discussion and debate with a colleague..\
>>>
>>> Warm reset is preferred as the bootrom keeps a score card to determine
>>> whether an spl image in the boot media failed or not.  If it failed,
>>> on a warm reset it will not retry the failed image.
>>
>> So what will it do ? Try a valid image from another slot at offset
>> +n*64kiB ?
> 
> Yes.  Or when the scorecard indicates 4 failures it will just stop.

I see.

>>>
>>> The other reason warm resets are preferred is for preservation of the
>>> dram contents.  On a warm reset it is possible to skip io configuration
>>> and dram calibration so that the contents can be saved.
>>
>> That's a good point.
>>
>> But here's a counterargument, what if you upgrade U-Boot ? Warm reset
>> will use the old SPL and the system will likely hang upon reboot ;-)
>>
>>>

 How do you point bootrom to run that snippet instead of whatever is in
 the OCRAM ?

>>>
>>> This code here
>>>

  > > > > > > + writel(ramboot_addr,
  > > > > > > +   _regs-
  > > > > > > >romcodegrp_warmramgrp_execution);
>>
>> Can't you just feed a function pointer pointing into some function which
>> is part of the SPL into that register then ? I think that'd do the same
>> trick, no ?
> 
> Yes, you could, but the idea of putting the code at the end of memory is to
> allow the onchip ram to be used for other things.

Well if you corrupt SPL and do a warm-reset, your system won't boot. We
had that already (and that's another +1 for just doing cold reset, always).

>>>
>>> writes the address to jump to on warm reset.  The register value
>>> is preserved through a warm reset.
>>
>> That's neat, I didn't know that.
>>
>>>


>>>
>>> All that said, i frankly do not believe for the CSEL=0 case
>>> there is any merit to doing the above.  Although it "preserves"
>>> the behaviour as compared to other CSEL values, i think a much
>>> simpler method is to, for the CSEL=0 case, just issue a cold reset.
>>>
>>> As in this case we are touching the clocks, i am not sure the
>>> use cases for a warm reset even hold (sdram preservation, etc).
>>> So i agree with you, and suggest only enabling the warm reset
>>> for cases where CSEL != 0.
>>>
>>> Unless there are objections, I will do just that and resubmit a
>>> patch. (which should now be just a few lines of code)
>>
>> See above, if this actually fixes issue, let's get it in. But in a
>> civilized fashion, no random ad-hoc asm if possible please :)
> 
> In v3 i just used the simpler method of not allowing warm resets for
> csel=0. This is far cleaner, and likely more reliable.

Hm, OK, it's fine either way for me.

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Sun, 2017-02-19 at 22:31 +0100, Marek Vasut wrote:
> On 02/18/2017 12:24 AM, Dalon Westergreen wrote:
> > 
> > On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
> > > 
> > > On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > > > > on warm resets.  To address this, the bootrom is configured to
> > > > > > > > > run a bit of code in the last 4KB of onchip ram on a warm
> > > > > > > > > reset.
> > > > > > > > > This code puts the PLLs in bypass, disables the bootrom
> > > > > > > > > configuration
> > > > > > > > > to run the code snippet, and issues a warm reset to run the
> > > > > > > > > bootrom.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Dalon Westergreen 
> > > > > > > > > 
> > > > > > > > > --
> > > > > > > > > Changes in V2:
> > > > > > > > >  - Fix checkpatch issues predominently due to whitespace
> > > > > > > > > issues
> > > > > > > > > ---
> > > > > > > > >  arch/arm/mach-socfpga/Makefile |  2 +-
> > > > > > > > >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26
> > > > > > > > > +++-
> > > > > > > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> > > > > > > > >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> > > > > > > > >  arch/arm/mach-socfpga/misc.c   | 27
> > > > > > > > > 
> > > > > > > > >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > > > > > > > > ++
> > > > > > > > >  6 files changed, 134 insertions(+), 3 deletions(-)
> > > > > > > > >  create mode 100644 arch/arm/mach-
> > > > > > > > > socfpga/reset_clock_manager.S
> > > > > > > > > 
> > > > > > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > > > > > > socfpga/Makefile
> > > > > > > > > index 809cd47..6876ccf 100644
> > > > > > > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > > > > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > > > > > > @@ -8,7 +8,7 @@
> > > > > > > > >  #
> > > > > > > > >  
> > > > > > > > >  obj-y+= misc.o timer.o reset_manager.o
> > > > > > > > > system_manager.o
> > > > > > > > > clock_manager.o \
> > > > > > > > > -    fpga_manager.o board.o
> > > > > > > > > +    fpga_manager.o board.o reset_clock_manager.o
> > > > > > > > >  
> > > > > > > > >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > > > > > > > >  
> > > > > > > > > diff --git a/arch/arm/mach-
> > > > > > > > > socfpga/include/mach/clock_manager.h
> > > > > > > > > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > > > index 803c926..78f63a4 100644
> > > > > > > > > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > > > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > > > @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const
> > > > > > > > > int
> > > > > > > > > osc);
> > > > > > > > >  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > > > > > > > >  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > > > > > > > >  
> > > > > > > > > +/* Onchip RAM functions for CSEL=0 */
> > > > > > > > > +void reset_clock_manager(void);
> > > > > > > > > +extern unsigned reset_clock_manager_size;
> > > > > > > > > +
> > > > > > > > >  /* Clock configuration accessors */
> > > > > > > > >  const struct cm_config * const cm_get_default_config(void);
> > > > > > > > > -#endif
> > > > > > > > >  
> > > > > > > > >  struct cm_config {
> > > > > > > > >   /* main group */
> > > > > > > > > @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
> > > > > > > > >   struct socfpga_clock_manager_altera altera;
> > > > > > > > >   u32 _pad_0xe8_0x200[70];
> > > > > > > > >  };
> > > > > > > > > +#endif
> > > > > > > > > +
> > > > > > > > > +#define CLKMGR_CTRL_ADDRESS 0x0
> > > > > > > > 
> > > > > > > > Is this the same as struct socfpga_clock_manager {} ?
> > > > > > > > Why ?
> > > > > > > It is, just defining offsets to use in the assembly calls
> > > > > > 
> > > > > > The asm is IMO not needed
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/18/2017 12:24 AM, Dalon Westergreen wrote:
> On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
>> On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
>>>
>>> On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:

 On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
>
>
> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
>>
>>
>>
>> On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
>>>
>>>
>>>
>>> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:




 When CSEL=0x0 the socfpga bootrom does not touch the clock
 configuration for the device.  This can lead to a boot failure
 on warm resets.  To address this, the bootrom is configured to
 run a bit of code in the last 4KB of onchip ram on a warm reset.
 This code puts the PLLs in bypass, disables the bootrom
 configuration
 to run the code snippet, and issues a warm reset to run the
 bootrom.

 Signed-off-by: Dalon Westergreen 

 --
 Changes in V2:
  - Fix checkpatch issues predominently due to whitespace issues
 ---
  arch/arm/mach-socfpga/Makefile |  2 +-
  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
  arch/arm/mach-socfpga/misc.c   | 27 
  arch/arm/mach-socfpga/reset_clock_manager.S| 71
 ++
  6 files changed, 134 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S

 diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
 socfpga/Makefile
 index 809cd47..6876ccf 100644
 --- a/arch/arm/mach-socfpga/Makefile
 +++ b/arch/arm/mach-socfpga/Makefile
 @@ -8,7 +8,7 @@
  #
  
  obj-y += misc.o timer.o reset_manager.o system_manager.o
 clock_manager.o \
 - fpga_manager.o board.o
 + fpga_manager.o board.o reset_clock_manager.o
  
  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
  
 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
 b/arch/arm/mach-socfpga/include/mach/clock_manager.h
 index 803c926..78f63a4 100644
 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
 +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
 @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int
 osc);
  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
  
 +/* Onchip RAM functions for CSEL=0 */
 +void reset_clock_manager(void);
 +extern unsigned reset_clock_manager_size;
 +
  /* Clock configuration accessors */
  const struct cm_config * const cm_get_default_config(void);
 -#endif
  
  struct cm_config {
/* main group */
 @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
struct socfpga_clock_manager_altera altera;
u32 _pad_0xe8_0x200[70];
  };
 +#endif
 +
 +#define CLKMGR_CTRL_ADDRESS 0x0
>>>
>>> Is this the same as struct socfpga_clock_manager {} ?
>>> Why ?
>> It is, just defining offsets to use in the assembly calls
>
> The asm is IMO not needed
>
>>
>>
>>
>>>
>>>
>>>
>>>




 +#define CLKMGR_BYPASS_ADDRESS 0x4
 +#define CLKMGR_INTER_ADDRESS 0x8
 +#define CLKMGR_INTREN_ADDRESS 0xc
 +#define CLKMGR_DBCTRL_ADDRESS 0x10
 +#define CLKMGR_STAT_ADDRESS 0x14
 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
 +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
 +
  
  #define CLKMGR_CTRL_SAFEMODE  (1 <<
 0)
  #define CLKMGR_CTRL_SAFEMODE_OFFSET   0
 @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK   0x
 
 0e
 00
  
 +/* Bypass Main and Per PLL, bypass source per input mux */
 +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
 + 
 
   
 
  
 +#define 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
> On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> > 
> > On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> > > 
> > > On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> > > > 
> > > > 
> > > > On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > > on warm resets.  To address this, the bootrom is configured to
> > > > > > > run a bit of code in the last 4KB of onchip ram on a warm reset.
> > > > > > > This code puts the PLLs in bypass, disables the bootrom
> > > > > > > configuration
> > > > > > > to run the code snippet, and issues a warm reset to run the
> > > > > > > bootrom.
> > > > > > > 
> > > > > > > Signed-off-by: Dalon Westergreen 
> > > > > > > 
> > > > > > > --
> > > > > > > Changes in V2:
> > > > > > >  - Fix checkpatch issues predominently due to whitespace issues
> > > > > > > ---
> > > > > > >  arch/arm/mach-socfpga/Makefile |  2 +-
> > > > > > >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
> > > > > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> > > > > > >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> > > > > > >  arch/arm/mach-socfpga/misc.c   | 27 
> > > > > > >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > > > > > > ++
> > > > > > >  6 files changed, 134 insertions(+), 3 deletions(-)
> > > > > > >  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> > > > > > > 
> > > > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > > > > socfpga/Makefile
> > > > > > > index 809cd47..6876ccf 100644
> > > > > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > > > > @@ -8,7 +8,7 @@
> > > > > > >  #
> > > > > > >  
> > > > > > >  obj-y+= misc.o timer.o reset_manager.o system_manager.o
> > > > > > > clock_manager.o \
> > > > > > > -    fpga_manager.o board.o
> > > > > > > +    fpga_manager.o board.o reset_clock_manager.o
> > > > > > >  
> > > > > > >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > > > > > >  
> > > > > > > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > index 803c926..78f63a4 100644
> > > > > > > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > > > @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int
> > > > > > > osc);
> > > > > > >  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > > > > > >  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > > > > > >  
> > > > > > > +/* Onchip RAM functions for CSEL=0 */
> > > > > > > +void reset_clock_manager(void);
> > > > > > > +extern unsigned reset_clock_manager_size;
> > > > > > > +
> > > > > > >  /* Clock configuration accessors */
> > > > > > >  const struct cm_config * const cm_get_default_config(void);
> > > > > > > -#endif
> > > > > > >  
> > > > > > >  struct cm_config {
> > > > > > >   /* main group */
> > > > > > > @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
> > > > > > >   struct socfpga_clock_manager_altera altera;
> > > > > > >   u32 _pad_0xe8_0x200[70];
> > > > > > >  };
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +#define CLKMGR_CTRL_ADDRESS 0x0
> > > > > > 
> > > > > > Is this the same as struct socfpga_clock_manager {} ?
> > > > > > Why ?
> > > > > It is, just defining offsets to use in the assembly calls
> > > > 
> > > > The asm is IMO not needed
> > > > 
> > > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > +#define CLKMGR_BYPASS_ADDRESS 0x4
> > > > > > > +#define CLKMGR_INTER_ADDRESS 0x8
> > > > > > > +#define CLKMGR_INTREN_ADDRESS 0xc
> > > > > > > +#define CLKMGR_DBCTRL_ADDRESS 0x10
> > > > > > > +#define CLKMGR_STAT_ADDRESS 0x14
> > > > > > > +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
> > > > > > > +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
> > > > > > > +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
> > > > > > > +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
> > > > > > > +
> > > > > > >  
> > > > > > >  #define CLKMGR_CTRL_SAFEMODE (1 <<
> > > > > > > 0)
> > > > > > >  #define CLKMGR_CTRL_SAFEMODE_OFFSET  0
> > > > > > > @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
> > 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
>> On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
>>>
>>> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:


 On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
>
>
> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
>>
>>
>>
>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>> configuration for the device.  This can lead to a boot failure
>> on warm resets.  To address this, the bootrom is configured to
>> run a bit of code in the last 4KB of onchip ram on a warm reset.
>> This code puts the PLLs in bypass, disables the bootrom configuration
>> to run the code snippet, and issues a warm reset to run the bootrom.
>>
>> Signed-off-by: Dalon Westergreen 
>>
>> --
>> Changes in V2:
>>  - Fix checkpatch issues predominently due to whitespace issues
>> ---
>>  arch/arm/mach-socfpga/Makefile |  2 +-
>>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>>  arch/arm/mach-socfpga/misc.c   | 27 
>>  arch/arm/mach-socfpga/reset_clock_manager.S| 71
>> ++
>>  6 files changed, 134 insertions(+), 3 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
>> socfpga/Makefile
>> index 809cd47..6876ccf 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -8,7 +8,7 @@
>>  #
>>  
>>  obj-y   += misc.o timer.o reset_manager.o system_manager.o
>> clock_manager.o \
>> -   fpga_manager.o board.o
>> +   fpga_manager.o board.o reset_clock_manager.o
>>  
>>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>>  
>> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> index 803c926..78f63a4 100644
>> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>> @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int
>> osc);
>>  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
>>  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
>>  
>> +/* Onchip RAM functions for CSEL=0 */
>> +void reset_clock_manager(void);
>> +extern unsigned reset_clock_manager_size;
>> +
>>  /* Clock configuration accessors */
>>  const struct cm_config * const cm_get_default_config(void);
>> -#endif
>>  
>>  struct cm_config {
>>  /* main group */
>> @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
>>  struct socfpga_clock_manager_altera altera;
>>  u32 _pad_0xe8_0x200[70];
>>  };
>> +#endif
>> +
>> +#define CLKMGR_CTRL_ADDRESS 0x0
>
> Is this the same as struct socfpga_clock_manager {} ?
> Why ?
 It is, just defining offsets to use in the assembly calls
>>>
>>> The asm is IMO not needed
>>>


>
>
>
>>
>>
>>
>> +#define CLKMGR_BYPASS_ADDRESS 0x4
>> +#define CLKMGR_INTER_ADDRESS 0x8
>> +#define CLKMGR_INTREN_ADDRESS 0xc
>> +#define CLKMGR_DBCTRL_ADDRESS 0x10
>> +#define CLKMGR_STAT_ADDRESS 0x14
>> +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
>> +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
>> +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
>> +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
>> +
>>  
>>  #define CLKMGR_CTRL_SAFEMODE(1 << 0)
>>  #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
>> @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
>>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET   9
>>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x
>> 0e
>> 00
>>  
>> +/* Bypass Main and Per PLL, bypass source per input mux */
>> +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
>> + 
>>   
>> 
>>  
>> +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
>> +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
>> +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
>> +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
>> +
>>  #endif /* _CLOCK_MANAGER_H_ */
>> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>> index 2f070f2..58d77fb 100644
>> --- 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> > 
> > On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > > 
> > > 
> > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > > 
> > > > 
> > > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > configuration for the device.  This can lead to a boot failure
> > > > > on warm resets.  To address this, the bootrom is configured to
> > > > > run a bit of code in the last 4KB of onchip ram on a warm reset.
> > > > > This code puts the PLLs in bypass, disables the bootrom configuration
> > > > > to run the code snippet, and issues a warm reset to run the bootrom.
> > > > > 
> > > > > Signed-off-by: Dalon Westergreen 
> > > > > 
> > > > > --
> > > > > Changes in V2:
> > > > >  - Fix checkpatch issues predominently due to whitespace issues
> > > > > ---
> > > > >  arch/arm/mach-socfpga/Makefile |  2 +-
> > > > >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
> > > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> > > > >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> > > > >  arch/arm/mach-socfpga/misc.c   | 27 
> > > > >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > > > > ++
> > > > >  6 files changed, 134 insertions(+), 3 deletions(-)
> > > > >  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> > > > > 
> > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > > socfpga/Makefile
> > > > > index 809cd47..6876ccf 100644
> > > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > > @@ -8,7 +8,7 @@
> > > > >  #
> > > > >  
> > > > >  obj-y+= misc.o timer.o reset_manager.o system_manager.o
> > > > > clock_manager.o \
> > > > > -    fpga_manager.o board.o
> > > > > +    fpga_manager.o board.o reset_clock_manager.o
> > > > >  
> > > > >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > > > >  
> > > > > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > index 803c926..78f63a4 100644
> > > > > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > > @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int
> > > > > osc);
> > > > >  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > > > >  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > > > >  
> > > > > +/* Onchip RAM functions for CSEL=0 */
> > > > > +void reset_clock_manager(void);
> > > > > +extern unsigned reset_clock_manager_size;
> > > > > +
> > > > >  /* Clock configuration accessors */
> > > > >  const struct cm_config * const cm_get_default_config(void);
> > > > > -#endif
> > > > >  
> > > > >  struct cm_config {
> > > > >   /* main group */
> > > > > @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
> > > > >   struct socfpga_clock_manager_altera altera;
> > > > >   u32 _pad_0xe8_0x200[70];
> > > > >  };
> > > > > +#endif
> > > > > +
> > > > > +#define CLKMGR_CTRL_ADDRESS 0x0
> > > > 
> > > > Is this the same as struct socfpga_clock_manager {} ?
> > > > Why ?
> > > It is, just defining offsets to use in the assembly calls
> > 
> > The asm is IMO not needed
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > 
> > > > > +#define CLKMGR_BYPASS_ADDRESS 0x4
> > > > > +#define CLKMGR_INTER_ADDRESS 0x8
> > > > > +#define CLKMGR_INTREN_ADDRESS 0xc
> > > > > +#define CLKMGR_DBCTRL_ADDRESS 0x10
> > > > > +#define CLKMGR_STAT_ADDRESS 0x14
> > > > > +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
> > > > > +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
> > > > > +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
> > > > > +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
> > > > > +
> > > > >  
> > > > >  #define CLKMGR_CTRL_SAFEMODE (1 << 0)
> > > > >  #define CLKMGR_CTRL_SAFEMODE_OFFSET  0
> > > > > @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
> > > > >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET9
> > > > >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK  0x
> > > > > 0e
> > > > > 00
> > > > >  
> > > > > +/* Bypass Main and Per PLL, bypass source per input mux */
> > > > > +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
> > > > > + 
> > > > >   
> > > > > 
> > > > >  
> > > > > +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
> > > > > +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
> > > > > +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
> > > > > +#define 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > 
> > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > 
> > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > configuration for the device.  This can lead to a boot failure
> > > > on warm resets.  To address this, the bootrom is configured to
> > > > run a bit of code in the last 4KB of onchip ram on a warm reset.
> > > > This code puts the PLLs in bypass, disables the bootrom configuration
> > > > to run the code snippet, and issues a warm reset to run the bootrom.
> > > > 
> > > > Signed-off-by: Dalon Westergreen 
> > > > 
> > > > --
> > > > Changes in V2:
> > > >  - Fix checkpatch issues predominently due to whitespace issues
> > > > ---
> > > >  arch/arm/mach-socfpga/Makefile |  2 +-
> > > >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
> > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> > > >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> > > >  arch/arm/mach-socfpga/misc.c   | 27 
> > > >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > > > ++
> > > >  6 files changed, 134 insertions(+), 3 deletions(-)
> > > >  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > socfpga/Makefile
> > > > index 809cd47..6876ccf 100644
> > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > @@ -8,7 +8,7 @@
> > > >  #
> > > >  
> > > >  obj-y  += misc.o timer.o reset_manager.o system_manager.o
> > > > clock_manager.o \
> > > > -      fpga_manager.o board.o
> > > > +      fpga_manager.o board.o reset_clock_manager.o
> > > >  
> > > >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > > >  
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > index 803c926..78f63a4 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > > > @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int osc);
> > > >  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> > > >  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> > > >  
> > > > +/* Onchip RAM functions for CSEL=0 */
> > > > +void reset_clock_manager(void);
> > > > +extern unsigned reset_clock_manager_size;
> > > > +
> > > >  /* Clock configuration accessors */
> > > >  const struct cm_config * const cm_get_default_config(void);
> > > > -#endif
> > > >  
> > > >  struct cm_config {
> > > >     /* main group */
> > > > @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
> > > >     struct socfpga_clock_manager_altera altera;
> > > >     u32 _pad_0xe8_0x200[70];
> > > >  };
> > > > +#endif
> > > > +
> > > > +#define CLKMGR_CTRL_ADDRESS 0x0
> > > 
> > > Is this the same as struct socfpga_clock_manager {} ?
> > > Why ?
> > It is, just defining offsets to use in the assembly calls
> 
> The asm is IMO not needed
> 
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > +#define CLKMGR_BYPASS_ADDRESS 0x4
> > > > +#define CLKMGR_INTER_ADDRESS 0x8
> > > > +#define CLKMGR_INTREN_ADDRESS 0xc
> > > > +#define CLKMGR_DBCTRL_ADDRESS 0x10
> > > > +#define CLKMGR_STAT_ADDRESS 0x14
> > > > +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
> > > > +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
> > > > +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
> > > > +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
> > > > +
> > > >  
> > > >  #define CLKMGR_CTRL_SAFEMODE   (1 << 0)
> > > >  #define CLKMGR_CTRL_SAFEMODE_OFFSET0
> > > > @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
> > > >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET  9
> > > >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK0x0e
> > > > 00
> > > >  
> > > > +/* Bypass Main and Per PLL, bypass source per input mux */
> > > > +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
> > > > +   
> > > > 
> > > >  
> > > > +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
> > > > +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
> > > > +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
> > > > +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
> > > > +
> > > >  #endif /* _CLOCK_MANAGER_H_ */
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > index 2f070f2..58d77fb 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > > > +++ 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
>> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
>>>
>>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>>> configuration for the device.  This can lead to a boot failure
>>> on warm resets.  To address this, the bootrom is configured to
>>> run a bit of code in the last 4KB of onchip ram on a warm reset.
>>> This code puts the PLLs in bypass, disables the bootrom configuration
>>> to run the code snippet, and issues a warm reset to run the bootrom.
>>>
>>> Signed-off-by: Dalon Westergreen 
>>>
>>> --
>>> Changes in V2:
>>>  - Fix checkpatch issues predominently due to whitespace issues
>>> ---
>>>  arch/arm/mach-socfpga/Makefile |  2 +-
>>>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>>>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>>>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>>>  arch/arm/mach-socfpga/misc.c   | 27 
>>>  arch/arm/mach-socfpga/reset_clock_manager.S| 71
>>> ++
>>>  6 files changed, 134 insertions(+), 3 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>> index 809cd47..6876ccf 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -8,7 +8,7 @@
>>>  #
>>>  
>>>  obj-y  += misc.o timer.o reset_manager.o system_manager.o
>>> clock_manager.o \
>>> -  fpga_manager.o board.o
>>> +  fpga_manager.o board.o reset_clock_manager.o
>>>  
>>>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>>>  
>>> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
>>> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>>> index 803c926..78f63a4 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
>>> @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int osc);
>>>  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
>>>  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
>>>  
>>> +/* Onchip RAM functions for CSEL=0 */
>>> +void reset_clock_manager(void);
>>> +extern unsigned reset_clock_manager_size;
>>> +
>>>  /* Clock configuration accessors */
>>>  const struct cm_config * const cm_get_default_config(void);
>>> -#endif
>>>  
>>>  struct cm_config {
>>> /* main group */
>>> @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
>>> struct socfpga_clock_manager_altera altera;
>>> u32 _pad_0xe8_0x200[70];
>>>  };
>>> +#endif
>>> +
>>> +#define CLKMGR_CTRL_ADDRESS 0x0
>>
>> Is this the same as struct socfpga_clock_manager {} ?
>> Why ?
> It is, just defining offsets to use in the assembly calls

The asm is IMO not needed

>>
>>>
>>> +#define CLKMGR_BYPASS_ADDRESS 0x4
>>> +#define CLKMGR_INTER_ADDRESS 0x8
>>> +#define CLKMGR_INTREN_ADDRESS 0xc
>>> +#define CLKMGR_DBCTRL_ADDRESS 0x10
>>> +#define CLKMGR_STAT_ADDRESS 0x14
>>> +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
>>> +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
>>> +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
>>> +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
>>> +
>>>  
>>>  #define CLKMGR_CTRL_SAFEMODE   (1 << 0)
>>>  #define CLKMGR_CTRL_SAFEMODE_OFFSET0
>>> @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
>>>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET  9
>>>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK0x0e00
>>>  
>>> +/* Bypass Main and Per PLL, bypass source per input mux */
>>> +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
>>> +   
>>>  
>>> +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
>>> +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
>>> +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
>>> +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
>>> +
>>>  #endif /* _CLOCK_MANAGER_H_ */
>>> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> index 2f070f2..58d77fb 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
>>> @@ -7,6 +7,7 @@
>>>  #ifndef_RESET_MANAGER_H_
>>>  #define_RESET_MANAGER_H_
>>>  
>>> +#ifndef __ASSEMBLY__
>>>  void reset_cpu(ulong addr);
>>>  void reset_deassert_peripherals_handoff(void);
>>>  
>>> @@ -28,6 +29,8 @@ struct socfpga_reset_manager {
>>> u32 padding2[12];
>>> u32 tstscratch;
>>>  };
>>> +#endif
>>> +
>>>  
>>>  #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
>>>  #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
>>> @@ -40,6 +43,7 @@ struct socfpga_reset_manager {
>>>   * and reset ID can be extracted 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > 
> > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > configuration for the device.  This can lead to a boot failure
> > on warm resets.  To address this, the bootrom is configured to
> > run a bit of code in the last 4KB of onchip ram on a warm reset.
> > This code puts the PLLs in bypass, disables the bootrom configuration
> > to run the code snippet, and issues a warm reset to run the bootrom.
> > 
> > Signed-off-by: Dalon Westergreen 
> > 
> > --
> > Changes in V2:
> >  - Fix checkpatch issues predominently due to whitespace issues
> > ---
> >  arch/arm/mach-socfpga/Makefile |  2 +-
> >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
> >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> >  arch/arm/mach-socfpga/misc.c   | 27 
> >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > ++
> >  6 files changed, 134 insertions(+), 3 deletions(-)
> >  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> > 
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> > index 809cd47..6876ccf 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -8,7 +8,7 @@
> >  #
> >  
> >  obj-y  += misc.o timer.o reset_manager.o system_manager.o
> > clock_manager.o \
> > -      fpga_manager.o board.o
> > +      fpga_manager.o board.o reset_clock_manager.o
> >  
> >  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> >  
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > index 803c926..78f63a4 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int osc);
> >  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
> >  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
> >  
> > +/* Onchip RAM functions for CSEL=0 */
> > +void reset_clock_manager(void);
> > +extern unsigned reset_clock_manager_size;
> > +
> >  /* Clock configuration accessors */
> >  const struct cm_config * const cm_get_default_config(void);
> > -#endif
> >  
> >  struct cm_config {
> >     /* main group */
> > @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
> >     struct socfpga_clock_manager_altera altera;
> >     u32 _pad_0xe8_0x200[70];
> >  };
> > +#endif
> > +
> > +#define CLKMGR_CTRL_ADDRESS 0x0
> 
> Is this the same as struct socfpga_clock_manager {} ?
> Why ?
It is, just defining offsets to use in the assembly calls
> 
> > 
> > +#define CLKMGR_BYPASS_ADDRESS 0x4
> > +#define CLKMGR_INTER_ADDRESS 0x8
> > +#define CLKMGR_INTREN_ADDRESS 0xc
> > +#define CLKMGR_DBCTRL_ADDRESS 0x10
> > +#define CLKMGR_STAT_ADDRESS 0x14
> > +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
> > +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
> > +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
> > +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
> > +
> >  
> >  #define CLKMGR_CTRL_SAFEMODE   (1 << 0)
> >  #define CLKMGR_CTRL_SAFEMODE_OFFSET0
> > @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
> >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET  9
> >  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK0x0e00
> >  
> > +/* Bypass Main and Per PLL, bypass source per input mux */
> > +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
> > +   
> >  
> > +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
> > +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
> > +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
> > +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
> > +
> >  #endif /* _CLOCK_MANAGER_H_ */
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 2f070f2..58d77fb 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -7,6 +7,7 @@
> >  #ifndef_RESET_MANAGER_H_
> >  #define_RESET_MANAGER_H_
> >  
> > +#ifndef __ASSEMBLY__
> >  void reset_cpu(ulong addr);
> >  void reset_deassert_peripherals_handoff(void);
> >  
> > @@ -28,6 +29,8 @@ struct socfpga_reset_manager {
> >     u32 padding2[12];
> >     u32 tstscratch;
> >  };
> > +#endif
> > +
> >  
> >  #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> >  #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
> > @@ -40,6 +43,7 @@ struct socfpga_reset_manager {
> >   * and reset ID can be extracted using the subsequent macros
> >   * RSTMGR_RESET() and RSTMGR_BANK().
> >   */
> 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device.  This can lead to a boot failure
> on warm resets.  To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a warm reset.
> This code puts the PLLs in bypass, disables the bootrom configuration
> to run the code snippet, and issues a warm reset to run the bootrom.
> 
> Signed-off-by: Dalon Westergreen 
> 
> --
> Changes in V2:
>  - Fix checkpatch issues predominently due to whitespace issues
> ---
>  arch/arm/mach-socfpga/Makefile |  2 +-
>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>  arch/arm/mach-socfpga/misc.c   | 27 
>  arch/arm/mach-socfpga/reset_clock_manager.S| 71 
> ++
>  6 files changed, 134 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 809cd47..6876ccf 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -8,7 +8,7 @@
>  #
>  
>  obj-y+= misc.o timer.o reset_manager.o system_manager.o 
> clock_manager.o \
> -fpga_manager.o board.o
> +fpga_manager.o board.o reset_clock_manager.o
>  
>  obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
>  
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 803c926..78f63a4 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int osc);
>  const unsigned int cm_get_f2s_per_ref_clk_hz(void);
>  const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
>  
> +/* Onchip RAM functions for CSEL=0 */
> +void reset_clock_manager(void);
> +extern unsigned reset_clock_manager_size;
> +
>  /* Clock configuration accessors */
>  const struct cm_config * const cm_get_default_config(void);
> -#endif
>  
>  struct cm_config {
>   /* main group */
> @@ -127,6 +130,19 @@ struct socfpga_clock_manager {
>   struct socfpga_clock_manager_altera altera;
>   u32 _pad_0xe8_0x200[70];
>  };
> +#endif
> +
> +#define CLKMGR_CTRL_ADDRESS 0x0

Is this the same as struct socfpga_clock_manager {} ?
Why ?

> +#define CLKMGR_BYPASS_ADDRESS 0x4
> +#define CLKMGR_INTER_ADDRESS 0x8
> +#define CLKMGR_INTREN_ADDRESS 0xc
> +#define CLKMGR_DBCTRL_ADDRESS 0x10
> +#define CLKMGR_STAT_ADDRESS 0x14
> +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
> +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
> +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
> +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
> +
>  
>  #define CLKMGR_CTRL_SAFEMODE (1 << 0)
>  #define CLKMGR_CTRL_SAFEMODE_OFFSET  0
> @@ -314,4 +330,12 @@ struct socfpga_clock_manager {
>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET9
>  #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK  0x0e00
>  
> +/* Bypass Main and Per PLL, bypass source per input mux */
> +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
> + 
>
> +#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
> +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
> +#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
> +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
> +
>  #endif /* _CLOCK_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
> b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 2f070f2..58d77fb 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -7,6 +7,7 @@
>  #ifndef  _RESET_MANAGER_H_
>  #define  _RESET_MANAGER_H_
>  
> +#ifndef __ASSEMBLY__
>  void reset_cpu(ulong addr);
>  void reset_deassert_peripherals_handoff(void);
>  
> @@ -28,6 +29,8 @@ struct socfpga_reset_manager {
>   u32 padding2[12];
>   u32 tstscratch;
>  };
> +#endif
> +
>  
>  #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
>  #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
> @@ -40,6 +43,7 @@ struct socfpga_reset_manager {
>   * and reset ID can be extracted using the subsequent macros
>   * RSTMGR_RESET() and RSTMGR_BANK().
>   */
> +#define RSTMGR_CTRL_OFFSET   4
>  #define RSTMGR_BANK_OFFSET   8
>  #define RSTMGR_BANK_MASK 0x7
>  #define RSTMGR_RESET_OFFSET  0
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
> b/arch/arm/mach-socfpga/include/mach/system_manager.h
> index c45edea..b89f269 100644
> --- 

Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Marek Vasut]

On 02/15/2017 07:56 AM, Chin Liang See wrote:
> On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
>> When CSEL=0x0 the socfpga bootrom does not touch the clock
>> configuration for the device.  This can lead to a boot failure
>> on warm resets.  To address this, the bootrom is configured to
>> run a bit of code in the last 4KB of onchip ram on a warm reset.
>> This code puts the PLLs in bypass, disables the bootrom configuration
>> to run the code snippet, and issues a warm reset to run the bootrom.
>>
>> Signed-off-by: Dalon Westergreen 
>>
>> --
>> Changes in V2:
>>  - Fix checkpatch issues predominently due to whitespace issues
>> ---
>>  arch/arm/mach-socfpga/Makefile |  2 +-
>>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>>  arch/arm/mach-socfpga/misc.c   | 27 
>>  arch/arm/mach-socfpga/reset_clock_manager.S| 71
>> ++
>>  6 files changed, 134 insertions(+), 3 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
>>
>>
> 
> Acked-by: Chin Liang See 

Sorry, in this state, definitelly

Naked-by: Marek Vasut 

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Chin Liang See]

On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote:
> When CSEL=0x0 the socfpga bootrom does not touch the clock
> configuration for the device.  This can lead to a boot failure
> on warm resets.  To address this, the bootrom is configured to
> run a bit of code in the last 4KB of onchip ram on a warm reset.
> This code puts the PLLs in bypass, disables the bootrom configuration
> to run the code snippet, and issues a warm reset to run the bootrom.
> 
> Signed-off-by: Dalon Westergreen 
> 
> --
> Changes in V2:
>  - Fix checkpatch issues predominently due to whitespace issues
> ---
>  arch/arm/mach-socfpga/Makefile |  2 +-
>  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
>  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
>  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
>  arch/arm/mach-socfpga/misc.c   | 27 
>  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> ++
>  6 files changed, 134 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
> 
> 

Acked-by: Chin Liang See 

Thanks
Chin Liang
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[U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

When CSEL=0x0 the socfpga bootrom does not touch the clock
configuration for the device.  This can lead to a boot failure
on warm resets.  To address this, the bootrom is configured to
run a bit of code in the last 4KB of onchip ram on a warm reset.
This code puts the PLLs in bypass, disables the bootrom configuration
to run the code snippet, and issues a warm reset to run the bootrom.

Signed-off-by: Dalon Westergreen 

--
Changes in V2:
 - Fix checkpatch issues predominently due to whitespace issues
---
 arch/arm/mach-socfpga/Makefile |  2 +-
 arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
 .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
 arch/arm/mach-socfpga/misc.c   | 27 
 arch/arm/mach-socfpga/reset_clock_manager.S| 71 ++
 6 files changed, 134 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..6876ccf 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,7 @@
 #
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-  fpga_manager.o board.o
+  fpga_manager.o board.o reset_clock_manager.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 803c926..78f63a4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -19,9 +19,12 @@ const unsigned int cm_get_osc_clk_hz(const int osc);
 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
 
+/* Onchip RAM functions for CSEL=0 */
+void reset_clock_manager(void);
+extern unsigned reset_clock_manager_size;
+
 /* Clock configuration accessors */
 const struct cm_config * const cm_get_default_config(void);
-#endif
 
 struct cm_config {
/* main group */
@@ -127,6 +130,19 @@ struct socfpga_clock_manager {
struct socfpga_clock_manager_altera altera;
u32 _pad_0xe8_0x200[70];
 };
+#endif
+
+#define CLKMGR_CTRL_ADDRESS 0x0
+#define CLKMGR_BYPASS_ADDRESS 0x4
+#define CLKMGR_INTER_ADDRESS 0x8
+#define CLKMGR_INTREN_ADDRESS 0xc
+#define CLKMGR_DBCTRL_ADDRESS 0x10
+#define CLKMGR_STAT_ADDRESS 0x14
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
+#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
+
 
 #define CLKMGR_CTRL_SAFEMODE   (1 << 0)
 #define CLKMGR_CTRL_SAFEMODE_OFFSET0
@@ -314,4 +330,12 @@ struct socfpga_clock_manager {
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET  9
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK0x0e00
 
+/* Bypass Main and Per PLL, bypass source per input mux */
+#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19
+   
 
+#define CLKMGR_MAINQSPICLK_RESET_VALUE  0x3
+#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3
+#define CLKMGR_PERQSPICLK_RESET_VALUE   0x1
+#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE  0x1
+
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..58d77fb 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -7,6 +7,7 @@
 #ifndef_RESET_MANAGER_H_
 #define_RESET_MANAGER_H_
 
+#ifndef __ASSEMBLY__
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
 
@@ -28,6 +29,8 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
 };
+#endif
+
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -40,6 +43,7 @@ struct socfpga_reset_manager {
  * and reset ID can be extracted using the subsequent macros
  * RSTMGR_RESET() and RSTMGR_BANK().
  */
+#define RSTMGR_CTRL_OFFSET 4
 #define RSTMGR_BANK_OFFSET 8
 #define RSTMGR_BANK_MASK   0x7
 #define RSTMGR_RESET_OFFSET0
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..b89f269 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -13,7 +13,6 @@ void sysmgr_pinmux_init(void);
 void sysmgr_config_warmrstcfgio(int enable);
 
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-#endif
 
 struct socfpga_system_manager {
/* System Manager Module */
@@ -115,6 +114,12 @@