Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-06 Thread Auer, Lukas
Hi Rick, On Tue, 2018-11-06 at 10:28 +0800, Rick Chen wrote: > Auer, Lukas 於 2018年11月4日 週日 > 下午10:21寫道： > > > > Hi Rick, > > > > On Thu, 2018-11-01 at 12:08 +0800, Andes wrote: > > > From: Rick Chen > > > > > > AndeStar RISC-V(V5) provide mcache_ctl register which > > > can configure I/D cach

Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-05 Thread Bin Meng
Hi Rick, On Tue, Nov 6, 2018 at 2:01 PM Rick Chen wrote: > > Hi Bin > > Bin Meng 於 2018年11月4日 週日 下午10:31寫道： > > > > Hi Rick, > > > > On Thu, Nov 1, 2018 at 12:10 PM Andes wrote: > > > > > > From: Rick Chen > > > > > > AndeStar RISC-V(V5) provide mcache_ctl register which > > > can configure I/

Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-05 Thread Rick Chen
Hi Bin Bin Meng 於 2018年11月4日 週日 下午10:31寫道： > > Hi Rick, > > On Thu, Nov 1, 2018 at 12:10 PM Andes wrote: > > > > From: Rick Chen > > > > AndeStar RISC-V(V5) provide mcache_ctl register which > > can configure I/D cache as enabled or disabled. > > > > This CSR will be encapsulated by CONFIG_RISC

Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-05 Thread Rick Chen
Auer, Lukas 於 2018年11月4日 週日 下午10:21寫道： > > Hi Rick, > > On Thu, 2018-11-01 at 12:08 +0800, Andes wrote: > > From: Rick Chen > > > > AndeStar RISC-V(V5) provide mcache_ctl register which > > can configure I/D cache as enabled or disabled. > > > > This CSR will be encapsulated by CONFIG_RISCV_NDS.

Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-04 Thread Bin Meng
Hi Rick, On Thu, Nov 1, 2018 at 12:10 PM Andes wrote: > > From: Rick Chen > > AndeStar RISC-V(V5) provide mcache_ctl register which > can configure I/D cache as enabled or disabled. > > This CSR will be encapsulated by CONFIG_RISCV_NDS. > If you want to configure cache on AndeStar V5 > AE350 pla

Re: [U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-04 Thread Auer, Lukas
Hi Rick, On Thu, 2018-11-01 at 12:08 +0800, Andes wrote: > From: Rick Chen > > AndeStar RISC-V(V5) provide mcache_ctl register which > can configure I/D cache as enabled or disabled. > > This CSR will be encapsulated by CONFIG_RISCV_NDS. > If you want to configure cache on AndeStar V5 > AE350 p

[U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

2018-10-31 Thread Andes
From: Rick Chen AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. T