To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See <cl...@altera.com>
Cc: Anatolij Gustschin <ag...@denx.de>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Heiko Schocher <h...@denx.de>
Cc: Tom Rini <tr...@ti.com>
---
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
.../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/designware_wdt.c | 73 ++++++++++++++++++++
include/configs/socfpga_cyclone5.h | 13 ++++
4 files changed, 88 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index 20f12e0..5f73824 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_UART1_ADDRESS 0xffc03000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 0000000..cb88844
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/utils.h>
+
+#define DW_WDT_CR 0x00
+#define DW_WDT_TORR 0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET 0x00
+#define DW_WDT_CR_RMOD_OFFSET 0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i > 15)
+ i = 15;
+ if (i < 0)
+ i = 0;
+
+ writel((i | (i<<4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \
+ (0x1 << DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val & 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+ (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index fc921ee..1b78ccb 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -207,6 +207,16 @@
#define CONFIG_ENV_IS_NOWHERE
/*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ 25000
+
+/*
* SPL "Second Program Loader" aka Initial Software
*/
@@ -238,4 +248,7 @@
/* Support for lib/libgeneric.o in SPL binary */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
#endif /* __CONFIG_H */
--
1.7.9.5
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