Re: [U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
于 2018年10月25日 GMT+08:00 下午5:23:01, Icenowy Zheng 写到: >This series tries to solve three issues we currently have on >Allwinner boards: >- The DRAM sizing routine can only cope with power-of-two sized DRAM. >- The DRAM sizing routine steps through all DRAM, possibly hitting >secure > memory. >- The SPL header versioning is quite strict and tends to break every >time > we need to update it. >- On some Allwinner SoCs the maximum supported DRAM size of the DRAM > controller is bigger than the accessible DRAM size of the CPU. > >So Andre Przywara adapted something along the lines of semantic >versioning[1], where we can add backwards-compatible changes to the SPL >header without breaking every tool. > >The second patch and the third patches introduces the version schema >and >does necessary refactors, then the fourth and the fifth patches prepare >for 3GiB memory support. The sixth patch finally enables the SPL header >to store the the DRAM size, and let U-Boot binary check which range is >accessible when picking the data. > >The first patch is a prepare for the other patches, as without it newly >introduced code will make H6 SPL overflow, which makes the patchset not >possible to test, as the only available 3GiB DRAM device now is the >3GiB version of Pine H64 sample. Jagan, could you have a check on this patchset and apply it? Thanks! > >Andre Przywara (3): > sunxi: Extend SPL header versioning > sunxi: board.c: refactor SPL header checks > sunxi: store DRAM size in SPL header > >Icenowy Zheng (3): > sunxi: disable Pine A64 model detection code on other boards > sunxi: map DRAM part with 3G size > sunxi: add Kconfig option for the maximum accessible DRAM > > arch/arm/include/asm/arch-sunxi/spl.h | 22 +--- > arch/arm/mach-sunxi/Kconfig | 18 +++ > arch/arm/mach-sunxi/board.c | 2 +- > board/sunxi/board.c | 74 ++- > configs/pine64_plus_defconfig | 1 + > 5 files changed, 97 insertions(+), 20 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
On Thu, Oct 25, 2018 at 05:23:01PM +0800, Icenowy Zheng wrote: > This series tries to solve three issues we currently have on > Allwinner boards: > - The DRAM sizing routine can only cope with power-of-two sized DRAM. > - The DRAM sizing routine steps through all DRAM, possibly hitting secure > memory. > - The SPL header versioning is quite strict and tends to break every time > we need to update it. > - On some Allwinner SoCs the maximum supported DRAM size of the DRAM > controller is bigger than the accessible DRAM size of the CPU. > > So Andre Przywara adapted something along the lines of semantic > versioning[1], where we can add backwards-compatible changes to the SPL > header without breaking every tool. > > The second patch and the third patches introduces the version schema and > does necessary refactors, then the fourth and the fifth patches prepare > for 3GiB memory support. The sixth patch finally enables the SPL header > to store the the DRAM size, and let U-Boot binary check which range is > accessible when picking the data. > > The first patch is a prepare for the other patches, as without it newly > introduced code will make H6 SPL overflow, which makes the patchset not > possible to test, as the only available 3GiB DRAM device now is the > 3GiB version of Pine H64 sample. For the whole series, Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
于 2018年10月25日 GMT+08:00 下午6:15:11, "André Przywara" 写到: >On 10/25/18 10:23 AM, Icenowy Zheng wrote: > >Hi Icenowy, > >thanks for picking this up, resending and adapting this! > >> This series tries to solve three issues we currently have on >> Allwinner boards: >> - The DRAM sizing routine can only cope with power-of-two sized DRAM. >> - The DRAM sizing routine steps through all DRAM, possibly hitting >secure >> memory. >> - The SPL header versioning is quite strict and tends to break every >time >> we need to update it. >> - On some Allwinner SoCs the maximum supported DRAM size of the DRAM >> controller is bigger than the accessible DRAM size of the CPU. >> >> So Andre Przywara adapted something along the lines of semantic >> versioning[1], where we can add backwards-compatible changes to the >SPL >> header without breaking every tool. >> >> The second patch and the third patches introduces the version schema >and >> does necessary refactors, then the fourth and the fifth patches >prepare >> for 3GiB memory support. The sixth patch finally enables the SPL >header >> to store the the DRAM size, and let U-Boot binary check which range >is >> accessible when picking the data. > >Out of curiosity: Do you know whether one can play around with the DRAM >controller's mapping registers to make the upper GB of a 4GB DRAM >accessible (so map 3-4GB to 0xc000 instead of 2-3GB)? To use >something like bank switching, maybe? This is not really aimed at any >upstream OS, I am just curious from a hacker's perspective. > >> The first patch is a prepare for the other patches, as without it >newly >> introduced code will make H6 SPL overflow, which makes the patchset >not >> possible to test, as the only available 3GiB DRAM device now is the >> 3GiB version of Pine H64 sample. > >I guess this tight memory situation is also the reason that you >disabled >PSCI_RESET in the defconfig? Do you know what causes the bigger memory >consumption for H6 boards? Is that the DRAM driver? For A64 I end up at >a rather comfortable 30KB SPL with my GCC 7.3.0 these days. Yes, the DRAM driver is ~2.5KiB larger. > >And just in case: If you run into size issues while testing and >developing, you can always disable ARMV8_SPL_EXCEPTION_VECTORS to gain >some additional KBs. I don't really want to make this permanent in a >defconfig, though. > >Cheers, >Andre. > >> >> Andre Przywara (3): >> sunxi: Extend SPL header versioning >> sunxi: board.c: refactor SPL header checks >> sunxi: store DRAM size in SPL header >> >> Icenowy Zheng (3): >> sunxi: disable Pine A64 model detection code on other boards >> sunxi: map DRAM part with 3G size >> sunxi: add Kconfig option for the maximum accessible DRAM >> >> arch/arm/include/asm/arch-sunxi/spl.h | 22 +--- >> arch/arm/mach-sunxi/Kconfig | 18 +++ >> arch/arm/mach-sunxi/board.c | 2 +- >> board/sunxi/board.c | 74 >++- >> configs/pine64_plus_defconfig | 1 + >> 5 files changed, 97 insertions(+), 20 deletions(-) >> ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
On 10/25/18 10:23 AM, Icenowy Zheng wrote: Hi Icenowy, thanks for picking this up, resending and adapting this! > This series tries to solve three issues we currently have on > Allwinner boards: > - The DRAM sizing routine can only cope with power-of-two sized DRAM. > - The DRAM sizing routine steps through all DRAM, possibly hitting secure > memory. > - The SPL header versioning is quite strict and tends to break every time > we need to update it. > - On some Allwinner SoCs the maximum supported DRAM size of the DRAM > controller is bigger than the accessible DRAM size of the CPU. > > So Andre Przywara adapted something along the lines of semantic > versioning[1], where we can add backwards-compatible changes to the SPL > header without breaking every tool. > > The second patch and the third patches introduces the version schema and > does necessary refactors, then the fourth and the fifth patches prepare > for 3GiB memory support. The sixth patch finally enables the SPL header > to store the the DRAM size, and let U-Boot binary check which range is > accessible when picking the data. Out of curiosity: Do you know whether one can play around with the DRAM controller's mapping registers to make the upper GB of a 4GB DRAM accessible (so map 3-4GB to 0xc000 instead of 2-3GB)? To use something like bank switching, maybe? This is not really aimed at any upstream OS, I am just curious from a hacker's perspective. > The first patch is a prepare for the other patches, as without it newly > introduced code will make H6 SPL overflow, which makes the patchset not > possible to test, as the only available 3GiB DRAM device now is the > 3GiB version of Pine H64 sample. I guess this tight memory situation is also the reason that you disabled PSCI_RESET in the defconfig? Do you know what causes the bigger memory consumption for H6 boards? Is that the DRAM driver? For A64 I end up at a rather comfortable 30KB SPL with my GCC 7.3.0 these days. And just in case: If you run into size issues while testing and developing, you can always disable ARMV8_SPL_EXCEPTION_VECTORS to gain some additional KBs. I don't really want to make this permanent in a defconfig, though. Cheers, Andre. > > Andre Przywara (3): > sunxi: Extend SPL header versioning > sunxi: board.c: refactor SPL header checks > sunxi: store DRAM size in SPL header > > Icenowy Zheng (3): > sunxi: disable Pine A64 model detection code on other boards > sunxi: map DRAM part with 3G size > sunxi: add Kconfig option for the maximum accessible DRAM > > arch/arm/include/asm/arch-sunxi/spl.h | 22 +--- > arch/arm/mach-sunxi/Kconfig | 18 +++ > arch/arm/mach-sunxi/board.c | 2 +- > board/sunxi/board.c | 74 ++- > configs/pine64_plus_defconfig | 1 + > 5 files changed, 97 insertions(+), 20 deletions(-) > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
This series tries to solve three issues we currently have on Allwinner boards: - The DRAM sizing routine can only cope with power-of-two sized DRAM. - The DRAM sizing routine steps through all DRAM, possibly hitting secure memory. - The SPL header versioning is quite strict and tends to break every time we need to update it. - On some Allwinner SoCs the maximum supported DRAM size of the DRAM controller is bigger than the accessible DRAM size of the CPU. So Andre Przywara adapted something along the lines of semantic versioning[1], where we can add backwards-compatible changes to the SPL header without breaking every tool. The second patch and the third patches introduces the version schema and does necessary refactors, then the fourth and the fifth patches prepare for 3GiB memory support. The sixth patch finally enables the SPL header to store the the DRAM size, and let U-Boot binary check which range is accessible when picking the data. The first patch is a prepare for the other patches, as without it newly introduced code will make H6 SPL overflow, which makes the patchset not possible to test, as the only available 3GiB DRAM device now is the 3GiB version of Pine H64 sample. Andre Przywara (3): sunxi: Extend SPL header versioning sunxi: board.c: refactor SPL header checks sunxi: store DRAM size in SPL header Icenowy Zheng (3): sunxi: disable Pine A64 model detection code on other boards sunxi: map DRAM part with 3G size sunxi: add Kconfig option for the maximum accessible DRAM arch/arm/include/asm/arch-sunxi/spl.h | 22 +--- arch/arm/mach-sunxi/Kconfig | 18 +++ arch/arm/mach-sunxi/board.c | 2 +- board/sunxi/board.c | 74 ++- configs/pine64_plus_defconfig | 1 + 5 files changed, 97 insertions(+), 20 deletions(-) -- 2.18.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
