Re: [U-Boot] [PATCH v2 2/2][Boards Need to Switch DM] spi: omap3_spi: Full dm conversion

2018-03-07 Thread Adam Ford 
On Tue, Mar 6, 2018 at 11:00 PM, Jagan Teki  wrote:
> omap3_spi now support dt along with platform data,
> respective boards need to switch into dm for the same.
>
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - Fixes omap3_spi_ofdata_to_platdata, build

Thanks for fixing that.
>

Tested-by: Adam Ford  #omap3_logic

>  drivers/spi/Kconfig  |  14 +-
>  drivers/spi/omap3_spi.c  | 342 
> +++
>  include/dm/platform_data/spi_omap3.h |  16 ++
>  3 files changed, 125 insertions(+), 247 deletions(-)
>  create mode 100644 include/dm/platform_data/spi_omap3.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index fd3f115ccf..56c337f664 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -99,6 +99,13 @@ config MVEBU_A3700_SPI
>   used to access the SPI NOR flash on platforms embedding this
>   Marvell IP core.
>
> +config OMAP3_SPI
> +   bool "McSPI driver for OMAP"
> +   help
> + SPI master controller for OMAP24XX and later Multichannel SPI
> + (McSPI). This driver be used to access SPI chips on platforms
> + embedding this OMAP3 McSPI IP core.
> +
>  config PIC32_SPI
> bool "Microchip PIC32 SPI driver"
> depends on MACH_PIC32
> @@ -291,11 +298,4 @@ config MXS_SPI
>   Enable the MXS SPI controller driver. This driver can be used
>   on the i.MX23 and i.MX28 SoCs.
>
> -config OMAP3_SPI
> -   bool "McSPI driver for OMAP"
> -   help
> - SPI master controller for OMAP24XX and later Multichannel SPI
> - (McSPI). This driver be used to access SPI chips on platforms
> - embedding this OMAP3 McSPI IP core.
> -
>  endmenu # menu "SPI Support"
> diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
> index b8a0bf495a..a6f1533985 100644
> --- a/drivers/spi/omap3_spi.c
> +++ b/drivers/spi/omap3_spi.c
> @@ -22,6 +22,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -109,9 +110,6 @@ struct mcspi {
>  };
>
>  struct omap3_spi_priv {
> -#ifndef CONFIG_DM_SPI
> -   struct spi_slave slave;
> -#endif
> struct mcspi *regs;
> unsigned int cs;
> unsigned int freq;
> @@ -312,12 +310,16 @@ static int omap3_spi_txrx(struct omap3_spi_priv *priv, 
> unsigned int len,
> return 0;
>  }
>
> -static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
> -const void *dout, void *din, unsigned long flags)
> +static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
>  {
> -   unsigned intlen;
> +   struct udevice *bus = dev->parent;
> +   struct omap3_spi_priv *priv = dev_get_priv(bus);
> +   struct dm_spi_slave_platdata *slave_plat = 
> dev_get_parent_platdata(dev);
> +   unsigned int len;
> int ret = -1;
>
> +   priv->cs = slave_plat->cs;
> if (priv->wordlen < 4 || priv->wordlen > 32) {
> printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
> return -1;
> @@ -353,78 +355,6 @@ static int _spi_xfer(struct omap3_spi_priv *priv, 
> unsigned int bitlen,
> return ret;
>  }
>
> -static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
> -{
> -   uint32_t confr, div = 0;
> -
> -   confr = readl(>regs->channel[priv->cs].chconf);
> -
> -   /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
> -   if (priv->freq) {
> -   while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
> -   > priv->freq)
> -   div++;
> -   } else {
> -div = 0xC;
> -   }
> -
> -   /* set clock divisor */
> -   confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
> -   confr |= div << 2;
> -
> -   omap3_spi_write_chconf(priv, confr);
> -}
> -
> -static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
> -{
> -   uint32_t confr;
> -
> -   confr = readl(>regs->channel[priv->cs].chconf);
> -
> -   /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
> -* REVISIT: this controller could support SPI_3WIRE mode.
> -*/
> -   if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
> -   confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
> -   confr |= OMAP3_MCSPI_CHCONF_DPE0;
> -   } else {
> -   confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
> -   confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
> -   }
> -
> -   /* set SPI mode 0..3 */
> -   confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
> -   if (priv->mode & SPI_CPHA)
> -   confr |= OMAP3_MCSPI_CHCONF_PHA;
> -   if (priv->mode & SPI_CPOL)
> -   confr |= OMAP3_MCSPI_CHCONF_POL;
> -
> -

[U-Boot] [PATCH v2 2/2][Boards Need to Switch DM] spi: omap3_spi: Full dm conversion

2018-03-06 Thread Jagan Teki 
omap3_spi now support dt along with platform data,
respective boards need to switch into dm for the same.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Fixes omap3_spi_ofdata_to_platdata, build 

 drivers/spi/Kconfig  |  14 +-
 drivers/spi/omap3_spi.c  | 342 +++
 include/dm/platform_data/spi_omap3.h |  16 ++
 3 files changed, 125 insertions(+), 247 deletions(-)
 create mode 100644 include/dm/platform_data/spi_omap3.h

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fd3f115ccf..56c337f664 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -99,6 +99,13 @@ config MVEBU_A3700_SPI
  used to access the SPI NOR flash on platforms embedding this
  Marvell IP core.
 
+config OMAP3_SPI
+   bool "McSPI driver for OMAP"
+   help
+ SPI master controller for OMAP24XX and later Multichannel SPI
+ (McSPI). This driver be used to access SPI chips on platforms
+ embedding this OMAP3 McSPI IP core.
+
 config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@@ -291,11 +298,4 @@ config MXS_SPI
  Enable the MXS SPI controller driver. This driver can be used
  on the i.MX23 and i.MX28 SoCs.
 
-config OMAP3_SPI
-   bool "McSPI driver for OMAP"
-   help
- SPI master controller for OMAP24XX and later Multichannel SPI
- (McSPI). This driver be used to access SPI chips on platforms
- embedding this OMAP3 McSPI IP core.
-
 endmenu # menu "SPI Support"
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index b8a0bf495a..a6f1533985 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -109,9 +110,6 @@ struct mcspi {
 };
 
 struct omap3_spi_priv {
-#ifndef CONFIG_DM_SPI
-   struct spi_slave slave;
-#endif
struct mcspi *regs;
unsigned int cs;
unsigned int freq;
@@ -312,12 +310,16 @@ static int omap3_spi_txrx(struct omap3_spi_priv *priv, 
unsigned int len,
return 0;
 }
 
-static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
-const void *dout, void *din, unsigned long flags)
+static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
 {
-   unsigned intlen;
+   struct udevice *bus = dev->parent;
+   struct omap3_spi_priv *priv = dev_get_priv(bus);
+   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   unsigned int len;
int ret = -1;
 
+   priv->cs = slave_plat->cs;
if (priv->wordlen < 4 || priv->wordlen > 32) {
printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
return -1;
@@ -353,78 +355,6 @@ static int _spi_xfer(struct omap3_spi_priv *priv, unsigned 
int bitlen,
return ret;
 }
 
-static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
-{
-   uint32_t confr, div = 0;
-
-   confr = readl(>regs->channel[priv->cs].chconf);
-
-   /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
-   if (priv->freq) {
-   while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
-   > priv->freq)
-   div++;
-   } else {
-div = 0xC;
-   }
-
-   /* set clock divisor */
-   confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
-   confr |= div << 2;
-
-   omap3_spi_write_chconf(priv, confr);
-}
-
-static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
-{
-   uint32_t confr;
-
-   confr = readl(>regs->channel[priv->cs].chconf);
-
-   /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
-* REVISIT: this controller could support SPI_3WIRE mode.
-*/
-   if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
-   confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
-   confr |= OMAP3_MCSPI_CHCONF_DPE0;
-   } else {
-   confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
-   confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
-   }
-
-   /* set SPI mode 0..3 */
-   confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
-   if (priv->mode & SPI_CPHA)
-   confr |= OMAP3_MCSPI_CHCONF_PHA;
-   if (priv->mode & SPI_CPOL)
-   confr |= OMAP3_MCSPI_CHCONF_POL;
-
-   /* set chipselect polarity; manage with FORCE */
-   if (!(priv->mode & SPI_CS_HIGH))
-   confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
-   else
-   confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
-
-   /* Transmit & receive mode */
-   confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
-
-   omap3_spi_write_chconf(priv, confr);
-}
-
-static void _omap3_spi_set_wordlen(struct