Re: [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
Hi Bin
>
> On Tue, Jul 9, 2019 at 5:34 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Add a v5l2 cache controller driver that is usually found on
> > Andes RISC-V ae350 platform. It will parse the cache settings
> > from the dtb.
> >
> > In this version tag and data ram control timing can be adjusted
> > by the requirement from the dtb.
> >
> > Signed-off-by: Rick Chen
> > Cc: Greentime Hu
> > Cc: KC Lin
> > ---
> > arch/riscv/include/asm/v5l2cache.h | 58 ++
> > drivers/cache/Kconfig | 9 +++
> > drivers/cache/Makefile | 1 +
> > drivers/cache/cache-v5l2.c | 121
> > +
> > 4 files changed, 189 insertions(+)
> > create mode 100644 arch/riscv/include/asm/v5l2cache.h
> > create mode 100644 drivers/cache/cache-v5l2.c
> >
> > diff --git a/arch/riscv/include/asm/v5l2cache.h
> > b/arch/riscv/include/asm/v5l2cache.h
> > new file mode 100644
> > index 000..28e40f8
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/v5l2cache.h
> > @@ -0,0 +1,58 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2019 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation
> > + */
> > +
> > +#ifndef _ASM_V5_L2CACHE_H
> > +#define _ASM_V5_L2CACHE_H
> > +
> > +struct l2cache {
> > + volatile u64configure;
> > + volatile u64control;
> > + volatile u64hpm0;
> > + volatile u64hpm1;
> > + volatile u64hpm2;
> > + volatile u64hpm3;
> > + volatile u64error_status;
> > + volatile u64ecc_error;
> > + volatile u64cctl_command0;
> > + volatile u64cctl_access_line0;
> > + volatile u64cctl_command1;
> > + volatile u64cctl_access_line1;
> > + volatile u64cctl_command2;
> > + volatile u64cctl_access_line2;
> > + volatile u64cctl_command3;
> > + volatile u64cctl_access_line4;
> > + volatile u64cctl_status;
> > +};
> > +
> > +/* Control Register */
> > +#define L2_ENABLE 0x1
> > +/* prefetch */
> > +#define IPREPETCH_OFF 3
> > +#define DPREPETCH_OFF 5
> > +#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
> > +#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
> > +/* tag ram */
> > +#define TRAMOCTL_OFF 8
> > +#define TRAMICTL_OFF 10
> > +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
> > +#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
> > +/* data ram */
> > +#define DRAMOCTL_OFF 11
> > +#define DRAMICTL_OFF 13
> > +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
> > +#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
> > +
> > +/* CCTL Command Register */
> > +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) *
> > 0x10)
> > +#define L2_WBINVAL_ALL 0x12
> > +
> > +/* CCTL Status Register */
> > +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
> > +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
> > +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
> > +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
> > +
> > +#endif /* _ASM_V5_L2CACHE_H */
> > diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> > index 24def7a..629039e 100644
> > --- a/drivers/cache/Kconfig
> > +++ b/drivers/cache/Kconfig
> > @@ -22,4 +22,13 @@ config L2X0_CACHE
> > ARMv7(32-bit) devices. The driver configures the cache settings
> > found in the device tree.
> >
> > +config V5L2_CACHE
> > + bool "Andes V5L2 cache driver"
> > + select CACHE
> > + depends on RISCV_NDS_CACHE
> > + help
> > + Support Andes V5L2 cache controller in AE350 platform.
> > + It will configure tag and data ram timing control from the
> > + device tree and enable L2 cache.
> > +
> > endmenu
> > diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> > index 9deb961..4a6458c 100644
> > --- a/drivers/cache/Makefile
> > +++ b/drivers/cache/Makefile
> > @@ -2,3 +2,4 @@
> > obj-$(CONFIG_CACHE) += cache-uclass.o
> > obj-$(CONFIG_SANDBOX) += sandbox_cache.o
> > obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> > +obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> > diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
> > new file mode 100644
> > index 000..dd1e72f
> > --- /dev/null
> > +++ b/drivers/cache/cache-v5l2.c
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +struct v5l2_plat {
> > + struct l2cache *regs;
> > +};
> > +
> > +int v5l2_enable(struct udevice *dev)
>
> This should be static.
OK
>
> > +{
> > + struct v5l2_plat *plat = dev_get_platdata(dev);
> > + volatile struct l2cache *regs = plat->regs;
> > +
> > + if (regs)
> > + s
Re: [U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
On Tue, Jul 9, 2019 at 5:34 PM Andes wrote:
>
> From: Rick Chen
>
> Add a v5l2 cache controller driver that is usually found on
> Andes RISC-V ae350 platform. It will parse the cache settings
> from the dtb.
>
> In this version tag and data ram control timing can be adjusted
> by the requirement from the dtb.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Cc: KC Lin
> ---
> arch/riscv/include/asm/v5l2cache.h | 58 ++
> drivers/cache/Kconfig | 9 +++
> drivers/cache/Makefile | 1 +
> drivers/cache/cache-v5l2.c | 121
> +
> 4 files changed, 189 insertions(+)
> create mode 100644 arch/riscv/include/asm/v5l2cache.h
> create mode 100644 drivers/cache/cache-v5l2.c
>
> diff --git a/arch/riscv/include/asm/v5l2cache.h
> b/arch/riscv/include/asm/v5l2cache.h
> new file mode 100644
> index 000..28e40f8
> --- /dev/null
> +++ b/arch/riscv/include/asm/v5l2cache.h
> @@ -0,0 +1,58 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation
> + */
> +
> +#ifndef _ASM_V5_L2CACHE_H
> +#define _ASM_V5_L2CACHE_H
> +
> +struct l2cache {
> + volatile u64configure;
> + volatile u64control;
> + volatile u64hpm0;
> + volatile u64hpm1;
> + volatile u64hpm2;
> + volatile u64hpm3;
> + volatile u64error_status;
> + volatile u64ecc_error;
> + volatile u64cctl_command0;
> + volatile u64cctl_access_line0;
> + volatile u64cctl_command1;
> + volatile u64cctl_access_line1;
> + volatile u64cctl_command2;
> + volatile u64cctl_access_line2;
> + volatile u64cctl_command3;
> + volatile u64cctl_access_line4;
> + volatile u64cctl_status;
> +};
> +
> +/* Control Register */
> +#define L2_ENABLE 0x1
> +/* prefetch */
> +#define IPREPETCH_OFF 3
> +#define DPREPETCH_OFF 5
> +#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
> +#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
> +/* tag ram */
> +#define TRAMOCTL_OFF 8
> +#define TRAMICTL_OFF 10
> +#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
> +#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
> +/* data ram */
> +#define DRAMOCTL_OFF 11
> +#define DRAMICTL_OFF 13
> +#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
> +#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
> +
> +/* CCTL Command Register */
> +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
> +#define L2_WBINVAL_ALL 0x12
> +
> +/* CCTL Status Register */
> +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
> +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
> +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
> +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
> +
> +#endif /* _ASM_V5_L2CACHE_H */
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> index 24def7a..629039e 100644
> --- a/drivers/cache/Kconfig
> +++ b/drivers/cache/Kconfig
> @@ -22,4 +22,13 @@ config L2X0_CACHE
> ARMv7(32-bit) devices. The driver configures the cache settings
> found in the device tree.
>
> +config V5L2_CACHE
> + bool "Andes V5L2 cache driver"
> + select CACHE
> + depends on RISCV_NDS_CACHE
> + help
> + Support Andes V5L2 cache controller in AE350 platform.
> + It will configure tag and data ram timing control from the
> + device tree and enable L2 cache.
> +
> endmenu
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> index 9deb961..4a6458c 100644
> --- a/drivers/cache/Makefile
> +++ b/drivers/cache/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_CACHE) += cache-uclass.o
> obj-$(CONFIG_SANDBOX) += sandbox_cache.o
> obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
> +obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
> new file mode 100644
> index 000..dd1e72f
> --- /dev/null
> +++ b/drivers/cache/cache-v5l2.c
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Andes Technology Corporation
> + * Rick Chen, Andes Technology Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct v5l2_plat {
> + struct l2cache *regs;
> +};
> +
> +int v5l2_enable(struct udevice *dev)
This should be static.
> +{
> + struct v5l2_plat *plat = dev_get_platdata(dev);
> + volatile struct l2cache *regs = plat->regs;
> +
> + if (regs)
> + setbits_le32(®s->control, L2_ENABLE);
> +
> + return 0;
> +}
> +
> +int v5l2_disable(struct udevice *dev)
ditto
> +{
> + struct v5l2_plat *plat = dev_get_platdata(dev);
> + volatile struct l2cache *regs = plat->regs;
> + u8 hart = gd->arch.boot_hart;
> + void __iomem *cctlcmd = (void __iome
[U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver
From: Rick Chen
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen
Cc: Greentime Hu
Cc: KC Lin
---
arch/riscv/include/asm/v5l2cache.h | 58 ++
drivers/cache/Kconfig | 9 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-v5l2.c | 121 +
4 files changed, 189 insertions(+)
create mode 100644 arch/riscv/include/asm/v5l2cache.h
create mode 100644 drivers/cache/cache-v5l2.c
diff --git a/arch/riscv/include/asm/v5l2cache.h
b/arch/riscv/include/asm/v5l2cache.h
new file mode 100644
index 000..28e40f8
--- /dev/null
+++ b/arch/riscv/include/asm/v5l2cache.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation
+ */
+
+#ifndef _ASM_V5_L2CACHE_H
+#define _ASM_V5_L2CACHE_H
+
+struct l2cache {
+ volatile u64configure;
+ volatile u64control;
+ volatile u64hpm0;
+ volatile u64hpm1;
+ volatile u64hpm2;
+ volatile u64hpm3;
+ volatile u64error_status;
+ volatile u64ecc_error;
+ volatile u64cctl_command0;
+ volatile u64cctl_access_line0;
+ volatile u64cctl_command1;
+ volatile u64cctl_access_line1;
+ volatile u64cctl_command2;
+ volatile u64cctl_access_line2;
+ volatile u64cctl_command3;
+ volatile u64cctl_access_line4;
+ volatile u64cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE 0x1
+/* prefetch */
+#define IPREPETCH_OFF 3
+#define DPREPETCH_OFF 5
+#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF 8
+#define TRAMICTL_OFF 10
+#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF 11
+#define DRAMICTL_OFF 13
+#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
+
+#endif /* _ASM_V5_L2CACHE_H */
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
ARMv7(32-bit) devices. The driver configures the cache settings
found in the device tree.
+config V5L2_CACHE
+ bool "Andes V5L2 cache driver"
+ select CACHE
+ depends on RISCV_NDS_CACHE
+ help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 000..dd1e72f
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+ struct l2cache *regs;
+};
+
+int v5l2_enable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+
+ if (regs)
+ setbits_le32(®s->control, L2_ENABLE);
+
+ return 0;
+}
+
+int v5l2_disable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+ u8 hart = gd->arch.boot_hart;
+ void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+ if ((regs) && (readl(®s->control) & L2_ENABLE)) {
+ writel(L2_WBINVAL_ALL, cctlcmd);
+
+ while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(®s->cctl_status) &
CCTL_STATUS_ILLEGAL(hart))) {
+ printf("L2 flush illegal! hanging...");
+
