Hi Michal,
On 28/05/19 09:45, Michal Simek wrote:
[...]
>> +static unsigned long psu_ddr_phybringup_data(void)
>> +{
>> +unsigned int regval = 0;
>> +unsigned int pll_retry = 10;
>> +unsigned int pll_locked = 0;
>> +
>> +while ((pll_retry > 0) && (!pll_locked)) {
>> +
On 24. 05. 19 15:40, Luca Ceresoli wrote:
> Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
> only publicly-available compatible carrier card. The SoM is based on the EV
> version of the Xilinx ZynqMP SoC+FPGA.
>
> The psu_init_gpl.c file has been generated from the board
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.
The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and
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