Add a driver for the audio hub. This is modelled as a misc device which
supports writing audio data from I2S.
Signed-off-by: Simon Glass
---
Changes in v2:
- Fix 'I2C' typo
arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 +++
drivers/sound/Kconfig| 9 +
drivers/sound/Makefile | 1 +
drivers/sound/tegra_ahub.c | 256 ++
4 files changed, 741 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra/tegra_ahub.h
create mode 100644 drivers/sound/tegra_ahub.c
diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h
b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
new file mode 100644
index 000..96d542a91ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
@@ -0,0 +1,475 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_ahub.h - Definitions for Tegra124 audio hub driver
+ * Taken from dc tegra_ahub.h
+ *
+ * Copyright 2018 Google LLC
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA_AHUB_H_
+#define _TEGRA_AHUB_H_
+
+/*
+ * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
+ * transmitted by a particular TX CIF.
+ */
+struct xbar_regs {
+ u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */
+ u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */
+ u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */
+ u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */
+
+ u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */
+ u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */
+ u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */
+ u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */
+ u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */
+
+ u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */
+ u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */
+ u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */
+ u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */
+ u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */
+ u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */
+
+ u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */
+ u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */
+
+ u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */
+ u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */
+ u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */
+ u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */
+ u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */
+ u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */
+
+ u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */
+ u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */
+ u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */
+ u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */
+
+ u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */
+};
+
+struct apbif_regs {
+ u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */
+ u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */
+ u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */
+ u32 channel0_txfifo;/* APBIF_CHANNEL0_TXFIFO */
+ u32 channel0_rxfifo;/* APBIF_CHANNEL0_RXFIFO */
+ u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */
+ u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */
+ u32 channel0_reserved0; /* RESERVED, offset 0x1C */
+ /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ u32 reserved123[3 * 8];
+ u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */
+ u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */
+ u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */
+ u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */
+ u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 spdif_live_stat;/* APBIF_SPDIF_LIVE_STATUS_0 */
+ u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */
+ u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */
+ u32 reserved_int_mask; /* RESERVED, offset 0xB8 */
+ u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */
+ u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */
+ u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */
+ u32
