Re: [U-Boot] [PATCH v2 5/8] spi: cadence_qspi: Clean up the #define names
On 11/25/2016 03:38 PM, Phil Edworthy wrote: > A lot of the #defines are for single bits in a register, where the > name has _MASK on the end. Since this can be used for both a mask > and the value, remove _MASK from them. > > Whilst doing so, also remove the unnecessary brackets around the > constants. > > Signed-off-by: Phil EdworthyI guess this is done in automated way ? Anyway, thanks ! Acked-by: Marek Vasut > --- > drivers/spi/cadence_qspi_apb.c | 86 > +- > 1 file changed, 43 insertions(+), 43 deletions(-) > > diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c > index cd46a15..e7d8320 100644 > --- a/drivers/spi/cadence_qspi_apb.c > +++ b/drivers/spi/cadence_qspi_apb.c > @@ -32,37 +32,37 @@ > #include > #include "cadence_qspi.h" > > -#define CQSPI_REG_POLL_US(1) /* 1us */ > -#define CQSPI_REG_RETRY (1) > -#define CQSPI_POLL_IDLE_RETRY(3) > +#define CQSPI_REG_POLL_US1 /* 1us */ > +#define CQSPI_REG_RETRY 1 > +#define CQSPI_POLL_IDLE_RETRY3 > > -#define CQSPI_FIFO_WIDTH (4) > +#define CQSPI_FIFO_WIDTH 4 > > -#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) > +#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50 > > /* Transfer mode */ > -#define CQSPI_INST_TYPE_SINGLE (0) > -#define CQSPI_INST_TYPE_DUAL (1) > -#define CQSPI_INST_TYPE_QUAD (2) > +#define CQSPI_INST_TYPE_SINGLE 0 > +#define CQSPI_INST_TYPE_DUAL 1 > +#define CQSPI_INST_TYPE_QUAD 2 > > -#define CQSPI_STIG_DATA_LEN_MAX (8) > - > -#define CQSPI_DUMMY_CLKS_PER_BYTE(8) > -#define CQSPI_DUMMY_BYTES_MAX(4) > +#define CQSPI_STIG_DATA_LEN_MAX 8 > > +#define CQSPI_DUMMY_CLKS_PER_BYTE8 > +#define CQSPI_DUMMY_BYTES_MAX4 > > #define CQSPI_REG_SRAM_FILL_THRESHOLD\ > ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) > + > / > * Controller's configuration and status register (offset from QSPI_BASE) > > / > #define CQSPI_REG_CONFIG0x00 > -#define CQSPI_REG_CONFIG_ENABLE_MASKBIT(0) > +#define CQSPI_REG_CONFIG_ENABLE BIT(0) > #define CQSPI_REG_CONFIG_CLK_POLBIT(1) > #define CQSPI_REG_CONFIG_CLK_PHABIT(2) > -#define CQSPI_REG_CONFIG_DIRECT_MASKBIT(7) > -#define CQSPI_REG_CONFIG_DECODE_MASKBIT(9) > -#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) > +#define CQSPI_REG_CONFIG_DIRECT BIT(7) > +#define CQSPI_REG_CONFIG_DECODE BIT(9) > +#define CQSPI_REG_CONFIG_XIP_IMMBIT(18) > #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 > #define CQSPI_REG_CONFIG_BAUD_LSB 19 > #define CQSPI_REG_CONFIG_IDLE_LSB 31 > @@ -123,18 +123,18 @@ > #define CQSPI_REG_IRQMASK 0x44 > > #define CQSPI_REG_INDIRECTRD0x60 > -#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) > -#define CQSPI_REG_INDIRECTRD_CANCEL_MASKBIT(1) > -#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASKBIT(2) > -#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) > +#define CQSPI_REG_INDIRECTRD_START BIT(0) > +#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1) > +#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) > +#define CQSPI_REG_INDIRECTRD_DONE BIT(5) > > #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 > #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 > #define CQSPI_REG_INDIRECTRDBYTES 0x6C > > #define CQSPI_REG_CMDCTRL 0x90 > -#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) > -#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) > +#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0) > +#define CQSPI_REG_CMDCTRL_INPROGRESSBIT(1) > #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 > #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 > #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 > @@ -150,10 +150,10 @@ > #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF > > #define CQSPI_REG_INDIRECTWR0x70 > -#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) > -#define
[U-Boot] [PATCH v2 5/8] spi: cadence_qspi: Clean up the #define names
A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy--- drivers/spi/cadence_qspi_apb.c | 86 +- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index cd46a15..e7d8320 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -32,37 +32,37 @@ #include #include "cadence_qspi.h" -#define CQSPI_REG_POLL_US (1) /* 1us */ -#define CQSPI_REG_RETRY(1) -#define CQSPI_POLL_IDLE_RETRY (3) +#define CQSPI_REG_POLL_US 1 /* 1us */ +#define CQSPI_REG_RETRY1 +#define CQSPI_POLL_IDLE_RETRY 3 -#define CQSPI_FIFO_WIDTH (4) +#define CQSPI_FIFO_WIDTH 4 -#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) +#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50 /* Transfer mode */ -#define CQSPI_INST_TYPE_SINGLE (0) -#define CQSPI_INST_TYPE_DUAL (1) -#define CQSPI_INST_TYPE_QUAD (2) +#define CQSPI_INST_TYPE_SINGLE 0 +#define CQSPI_INST_TYPE_DUAL 1 +#define CQSPI_INST_TYPE_QUAD 2 -#define CQSPI_STIG_DATA_LEN_MAX(8) - -#define CQSPI_DUMMY_CLKS_PER_BYTE (8) -#define CQSPI_DUMMY_BYTES_MAX (4) +#define CQSPI_STIG_DATA_LEN_MAX8 +#define CQSPI_DUMMY_CLKS_PER_BYTE 8 +#define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_REG_SRAM_FILL_THRESHOLD \ ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) + / * Controller's configuration and status register (offset from QSPI_BASE) / #defineCQSPI_REG_CONFIG0x00 -#defineCQSPI_REG_CONFIG_ENABLE_MASKBIT(0) +#defineCQSPI_REG_CONFIG_ENABLE BIT(0) #defineCQSPI_REG_CONFIG_CLK_POLBIT(1) #defineCQSPI_REG_CONFIG_CLK_PHABIT(2) -#defineCQSPI_REG_CONFIG_DIRECT_MASKBIT(7) -#defineCQSPI_REG_CONFIG_DECODE_MASKBIT(9) -#defineCQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) +#defineCQSPI_REG_CONFIG_DIRECT BIT(7) +#defineCQSPI_REG_CONFIG_DECODE BIT(9) +#defineCQSPI_REG_CONFIG_XIP_IMMBIT(18) #defineCQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #defineCQSPI_REG_CONFIG_BAUD_LSB 19 #defineCQSPI_REG_CONFIG_IDLE_LSB 31 @@ -123,18 +123,18 @@ #defineCQSPI_REG_IRQMASK 0x44 #defineCQSPI_REG_INDIRECTRD0x60 -#defineCQSPI_REG_INDIRECTRD_START_MASK BIT(0) -#defineCQSPI_REG_INDIRECTRD_CANCEL_MASKBIT(1) -#defineCQSPI_REG_INDIRECTRD_INPROGRESS_MASKBIT(2) -#defineCQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) +#defineCQSPI_REG_INDIRECTRD_START BIT(0) +#defineCQSPI_REG_INDIRECTRD_CANCEL BIT(1) +#defineCQSPI_REG_INDIRECTRD_INPROGRESS BIT(2) +#defineCQSPI_REG_INDIRECTRD_DONE BIT(5) #defineCQSPI_REG_INDIRECTRDWATERMARK 0x64 #defineCQSPI_REG_INDIRECTRDSTARTADDR 0x68 #defineCQSPI_REG_INDIRECTRDBYTES 0x6C #defineCQSPI_REG_CMDCTRL 0x90 -#defineCQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) -#defineCQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) +#defineCQSPI_REG_CMDCTRL_EXECUTE BIT(0) +#defineCQSPI_REG_CMDCTRL_INPROGRESSBIT(1) #defineCQSPI_REG_CMDCTRL_DUMMY_LSB 7 #defineCQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 #defineCQSPI_REG_CMDCTRL_WR_EN_LSB 15 @@ -150,10 +150,10 @@ #defineCQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF #defineCQSPI_REG_INDIRECTWR0x70 -#defineCQSPI_REG_INDIRECTWR_START_MASK BIT(0) -#defineCQSPI_REG_INDIRECTWR_CANCEL_MASKBIT(1) -#defineCQSPI_REG_INDIRECTWR_INPROGRESS_MASKBIT(2) -#defineCQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) +#defineCQSPI_REG_INDIRECTWR_START BIT(0) +#defineCQSPI_REG_INDIRECTWR_CANCEL BIT(1) +#define