Re: [U-Boot] [PATCH v3 01/11] spi: cadence_qspi: Fix clearing of pol/pha bits
On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthywrote: > Or'ing together bit positions is clearly wrong. > > Signed-off-by: Phil Edworthy > Acked-by: Marek Vasut Reviewed-by: Jagan Teki thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/11] spi: cadence_qspi: Fix clearing of pol/pha bits
Or'ing together bit positions is clearly wrong. Signed-off-by: Phil EdworthyAcked-by: Marek Vasut --- v3: - No change. v2: - No change. --- drivers/spi/cadence_qspi_apb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c..2403e71 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); - reg &= ~(1 << - (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB); reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot