Re: [U-Boot] [PATCH v3 02/11] spi: cadence_qspi: Fix baud rate calculation

[Jagan Teki]

On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
 wrote:
> With the existing code, when the requested SPI clock rate is near
> to the lowest that can be achieved by the hardware (max divider
> of the ref clock is 32), the generated clock rate is wrong.
> For example, with a 50MHz ref clock, when asked for anything less
> than a 1.5MHz SPI clock, the code sets up the divider to generate
> 25MHz.
>
> This change fixes the calculation.
>
> Signed-off-by: Phil Edworthy 

Perhaps you missed, Marek Acked-by tag on previous version, don't
worry will add while applying if any.

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH v3 02/11] spi: cadence_qspi: Fix baud rate calculation

[Phil Edworthy]

With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.

This change fixes the calculation.

Signed-off-by: Phil Edworthy 
---
v3:
 - Use single line DIV_ROUND_UP instead of two
v2:
 - Use the DIV_ROUND_UP macro
---
 drivers/spi/cadence_qspi_apb.c | 22 ++
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2403e71..b5c664f 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -273,22 +273,12 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 
-   div = ref_clk_hz / sclk_hz;
-
-   if (div > 32)
-   div = 32;
-
-   /* Check if even number. */
-   if ((div & 1)) {
-   div = (div / 2);
-   } else {
-   if (ref_clk_hz % sclk_hz)
-   /* ensure generated SCLK doesn't exceed user
-   specified sclk_hz */
-   div = (div / 2);
-   else
-   div = (div / 2) - 1;
-   }
+   /*
+* The baud_div field in the config reg is 4 bits, and the ref clock is
+* divided by 2 * (baud_div + 1). Round up the divider to ensure the
+* SPI clock rate is less than or equal to the requested clock rate.
+*/
+   div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 
debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
  ref_clk_hz, sclk_hz, div);
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot