Re: [U-Boot] [PATCH v3 02/16] FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

On Aug 29, 2008, at 5:16 PM, Peter Tyser wrote: > Hello, > > [snip] > >> + >> +/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ >> +static void set_ddr_sdram_cfg_2(fsl_memctl_config_regs_t *ddr, >> + const memctl_options_t *popts) >> +{ >> +unsigned int frc_

Re: [U-Boot] [PATCH v3 02/16] FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

Hello, [snip] > + > +/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ > +static void set_ddr_sdram_cfg_2(fsl_memctl_config_regs_t *ddr, > +const memctl_options_t *popts) > +{ > + unsigned int frc_sr = 0;/* Force self refresh */ > + unsigned int

Re: [U-Boot] [PATCH v3 02/16] FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

Dear Kumar Gala, In message <[EMAIL PROTECTED]> you wrote: > Signed-off-by: James Yang <[EMAIL PROTECTED]> > Signed-off-by: Jon Loeliger <[EMAIL PROTECTED]> > Signed-off-by: Becky Bruce <[EMAIL PROTECTED]> > Signed-off-by: Ed Swarthout <[EMAIL PROTECTED]> > Signed-off-by: Kumar Gala <[EMAIL PROTEC