This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the
On Wed, 18 Feb 2015 15:16:28 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for the ARM errata 799270 which says
If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in
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