Re: [U-Boot] [PATCH v3 08/12] x86: dts: Add SPI flash MRC details for chromebook_link

2015-01-24 Thread Simon Glass
On 19 January 2015 at 22:16, Simon Glass s...@chromium.org wrote: Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass s...@chromium.org --- Changes

[U-Boot] [PATCH v3 08/12] x86: dts: Add SPI flash MRC details for chromebook_link

2015-01-19 Thread Simon Glass
Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v3: - Drop accidental creation of link.dts due to bad rebase Changes