Re: [U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-01 Thread Rick Chen 
Hi Lukas

Auer, Lukas  於 2019年4月1日 週一 下午5:09寫道：
>
> Hi Rick,
>
> On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > From: Rick Chen 
> >
> > The platform-Level Machine Timer (PLMT) block
> > holds memory-mapped mtime register associated
> > with timer tick.
> >
> > This driver implements the riscv_get_time() which
> > is required by the generic RISC-V timer driver.
> >
> > Signed-off-by: Rick Chen 
> > Cc: Greentime Hu 
> > Reviewed-by: Bin Meng 
> > ---
> > V3:
> >  - Add a space before (PLMT).
> >
> >  arch/riscv/Kconfig   |  9 ++
> >  arch/riscv/include/asm/global_data.h |  3 ++
> >  arch/riscv/include/asm/syscon.h  |  1 +
> >  arch/riscv/lib/Makefile  |  1 +
> >  arch/riscv/lib/andes_plmt.c  | 53 
> > 
> >  5 files changed, 67 insertions(+)
> >  create mode 100644 arch/riscv/lib/andes_plmt.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 511768b..ae8ff7b 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -118,6 +118,15 @@ config ANDES_PLIC
> > The Andes PLIC block holds memory-mapped claim and pending registers
> > associated with software interrupt.
> >
> > +config ANDES_PLMT
> > + bool
> > + depends on RISCV_MMODE
> > + select REGMAP
> > + select SYSCON
> > + help
> > +   The Andes PLMT block holds memory-mapped mtime register
> > +   associated with timer tick.
> > +
> >  config RISCV_RDTIME
> >   bool
> >   default y if RISCV_SMODE
> > diff --git a/arch/riscv/include/asm/global_data.h 
> > b/arch/riscv/include/asm/global_data.h
> > index b867910..dffcd45 100644
> > --- a/arch/riscv/include/asm/global_data.h
> > +++ b/arch/riscv/include/asm/global_data.h
> > @@ -21,6 +21,9 @@ struct arch_global_data {
> >  #ifdef CONFIG_ANDES_PLIC
> >   void __iomem *plic; /* plic base address */
> >  #endif
> > +#ifdef CONFIG_ANDES_PLMT
> > + void __iomem *plmt; /* plmt base address */
> > +#endif
> >  #ifdef CONFIG_SMP
> >   struct ipi_data ipi[CONFIG_NR_CPUS];
> >  #endif
> > diff --git a/arch/riscv/include/asm/syscon.h 
> > b/arch/riscv/include/asm/syscon.h
> > index c1b4b86..6e12574 100644
> > --- a/arch/riscv/include/asm/syscon.h
> > +++ b/arch/riscv/include/asm/syscon.h
> > @@ -14,6 +14,7 @@ enum {
> >   RISCV_NONE,
> >   RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> >   RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) 
> > */
> > + RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
> >  };
> >
> >  #endif /* _ASM_SYSCON_H */
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 1bf554b..1c332db 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -12,6 +12,7 @@ obj-y   += cache.o
> >  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
> >  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> >  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > +obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
> >  obj-y+= interrupts.o
> >  obj-y+= reset.o
> >  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> > diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> > new file mode 100644
> > index 000..12d7e0e
> > --- /dev/null
> > +++ b/arch/riscv/lib/andes_plmt.c
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019, Rick Chen 
> > + *
> > + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> > + * The PLMT block holds memory-mapped mtime register
> > + * associated with timer tick.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* mtime register */
> > +#define MTIME_REG(base)  ((ulong)(base))
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define PLMT_BASE_GET(void)  \
> > + do {\
> > + long *ret;  \
> > + \
> > + if (!gd->arch.plmt) {   \
> > + ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> > + if (IS_ERR(ret))\
> > + return PTR_ERR(ret);\
> > + gd->arch.plmt = ret;\
> > + }   \
> > + } while (0)
> > +
> > +int riscv_get_time(u64 *time)
> > +{
> > + PLMT_BASE_GET();
> > +
> > + *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> > +
> > + return 0;
> > +}
> > +
> > +static const struct udevice_id nds_plmt_ids[] = {
> > + { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
>
> Would a compatible string of "andes,plmt0" be

Re: [U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-01 Thread Auer, Lukas 
Hi Rick,

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen 
> 
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
> 
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
> 
> Signed-off-by: Rick Chen 
> Cc: Greentime Hu 
> Reviewed-by: Bin Meng 
> ---
> V3:
>  - Add a space before (PLMT).
> 
>  arch/riscv/Kconfig   |  9 ++
>  arch/riscv/include/asm/global_data.h |  3 ++
>  arch/riscv/include/asm/syscon.h  |  1 +
>  arch/riscv/lib/Makefile  |  1 +
>  arch/riscv/lib/andes_plmt.c  | 53 
> 
>  5 files changed, 67 insertions(+)
>  create mode 100644 arch/riscv/lib/andes_plmt.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 511768b..ae8ff7b 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -118,6 +118,15 @@ config ANDES_PLIC
> The Andes PLIC block holds memory-mapped claim and pending registers
> associated with software interrupt.
>  
> +config ANDES_PLMT
> + bool
> + depends on RISCV_MMODE
> + select REGMAP
> + select SYSCON
> + help
> +   The Andes PLMT block holds memory-mapped mtime register
> +   associated with timer tick.
> +
>  config RISCV_RDTIME
>   bool
>   default y if RISCV_SMODE
> diff --git a/arch/riscv/include/asm/global_data.h 
> b/arch/riscv/include/asm/global_data.h
> index b867910..dffcd45 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -21,6 +21,9 @@ struct arch_global_data {
>  #ifdef CONFIG_ANDES_PLIC
>   void __iomem *plic; /* plic base address */
>  #endif
> +#ifdef CONFIG_ANDES_PLMT
> + void __iomem *plmt; /* plmt base address */
> +#endif
>  #ifdef CONFIG_SMP
>   struct ipi_data ipi[CONFIG_NR_CPUS];
>  #endif
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index c1b4b86..6e12574 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -14,6 +14,7 @@ enum {
>   RISCV_NONE,
>   RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
>   RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
> + RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
>  };
>  
>  #endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 1bf554b..1c332db 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -12,6 +12,7 @@ obj-y   += cache.o
>  obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
>  obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
>  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> +obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
>  obj-y+= interrupts.o
>  obj-y+= reset.o
>  obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
> new file mode 100644
> index 000..12d7e0e
> --- /dev/null
> +++ b/arch/riscv/lib/andes_plmt.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019, Rick Chen 
> + *
> + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
> + * The PLMT block holds memory-mapped mtime register
> + * associated with timer tick.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* mtime register */
> +#define MTIME_REG(base)  ((ulong)(base))
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define PLMT_BASE_GET(void)  \
> + do {\
> + long *ret;  \
> + \
> + if (!gd->arch.plmt) {   \
> + ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
> + if (IS_ERR(ret))\
> + return PTR_ERR(ret);\
> + gd->arch.plmt = ret;\
> + }   \
> + } while (0)
> +
> +int riscv_get_time(u64 *time)
> +{
> + PLMT_BASE_GET();
> +
> + *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
> +
> + return 0;
> +}
> +
> +static const struct udevice_id nds_plmt_ids[] = {
> + { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },

Would a compatible string of "andes,plmt0" be more suitable?

> + { }
> +};
> +
> +U_BOOT_DRIVER(nds_plmt) = {
> + .name   = "nds_plmt",

nit: andes_plmt

Thanks,
Lukas

> + .id = UCLASS_SYSCON,
> + .of_match   = nds_plmt_ids,
> + .flags  = DM_FLAG_PRE_RELOC,
> +};
___
U-Boot

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-01 Thread Andes 
From: Rick Chen 

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
V3:
 - Add a space before (PLMT).

 arch/riscv/Kconfig   |  9 ++
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h  |  1 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/andes_plmt.c  | 53 
 5 files changed, 67 insertions(+)
 create mode 100644 arch/riscv/lib/andes_plmt.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768b..ae8ff7b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
+config ANDES_PLMT
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b867910..dffcd45 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+   void __iomem *plmt; /* plmt base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index c1b4b86..6e12574 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -14,6 +14,7 @@ enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
+   RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1bf554b..1c332db 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
new file mode 100644
index 000..12d7e0e
--- /dev/null
+++ b/arch/riscv/lib/andes_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* mtime register */
+#define MTIME_REG(base)((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plmt) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plmt = ret;\
+   }   \
+   } while (0)
+
+int riscv_get_time(u64 *time)
+{
+   PLMT_BASE_GET();
+
+   *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+   return 0;
+}
+
+static const struct udevice_id nds_plmt_ids[] = {
+   { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+   { }
+};
+
+U_BOOT_DRIVER(nds_plmt) = {
+   .name   = "nds_plmt",
+   .id = UCLASS_SYSCON,
+   .of_match   = nds_plmt_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

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