Re: [U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote: > From: Rick Chen > > Limit the cache configuration only can be supported in M mode. > It can not be manipulated in S mode. > > Signed-off-by: Rick Chen > Cc: Greentime Hu > Reviewed-by: Bin Meng > --- > arch/riscv/cpu/ax25/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Lukas Auer ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode
From: Rick Chen Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 68bd4e9..6b4b92e 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -14,6 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
