Re: [U-Boot] [PATCH v4 1/3] armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus

On 07/24/2017 11:34 PM, Ashish Kumar wrote: > CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which > provides full cache coherency between two clusters of multi-core > CPUs and I/O coherency for devices and I/O masters. > > This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and >

[U-Boot] [PATCH v4 1/3] armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and moves existing register space definaton of CCI-400 bus