Re: [U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node
On 4/3/19 7:45 AM, Ley Foon Tan wrote: > Merge qspi dts node from Linux. > Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10) > > Add -u-boot.dtsi files for non Linux dts properties and > update properties for Uboot. > - add u-boot,dm-pre-reloc > - add alias for spi0 > - change compatible for flash > - support quad read and quad write > - change maximum frequency to 100MHz > > Tested on Stratix 10 SoC devkit. > SOCFPGA_STRATIX10 # sf probe 0:0 > SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 > MiB > > Signed-off-by: Ley Foon Tan Applied, thanks. -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node
On Tue, Apr 9, 2019 at 7:33 AM Ley Foon Tan wrote:
>
> On Wed, Apr 3, 2019 at 1:45 PM Ley Foon Tan wrote:
> >
> > Merge qspi dts node from Linux.
> > Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for
> > Stratix10)
> >
> > Add -u-boot.dtsi files for non Linux dts properties and
> > update properties for Uboot.
> > - add u-boot,dm-pre-reloc
> > - add alias for spi0
> > - change compatible for flash
> > - support quad read and quad write
> > - change maximum frequency to 100MHz
> >
> > Tested on Stratix 10 SoC devkit.
> > SOCFPGA_STRATIX10 # sf probe 0:0
> > SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total
> > 256 MiB
> >
> > Signed-off-by: Ley Foon Tan
Looks good to me now.
Reviewed-by: Simon Goldschmidt >
> > ---
> > v4->v5:
> > - Add -u-boot.dtsi
> > - Update commit message with Linux commit ID
> >
> > v3->v4:
> > - Add qspi node to dtsi based on alphabetical order
> > - Add spi-tx-bus-width and spi-rx-bus-width
> >
> > v2->v3:
> > - Change flash compatible to "jedec,spi-nor"
> > - Change spi-max-frequency to 100MHz
> > ---
> > arch/arm/dts/socfpga_stratix10.dtsi | 13 +++
> > .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 25 +
> > arch/arm/dts/socfpga_stratix10_socdk.dts | 35 +++
> > 3 files changed, 73 insertions(+)
> > mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi
> > create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
> >
> > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
> > b/arch/arm/dts/socfpga_stratix10.dtsi
> > old mode 100644
> > new mode 100755
> > index ee93725d648..d1ae2fabae0
> > --- a/arch/arm/dts/socfpga_stratix10.dtsi
> > +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> > @@ -237,6 +237,19 @@
> > reg = <0xffe0 0x10>;
> > };
> >
> > + qspi: spi@ff8d2000 {
> > + compatible = "cdns,qspi-nor";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0xff8d2000 0x100>,
> > + <0xff90 0x10>;
> > + interrupts = <0 3 4>;
> > + cdns,fifo-depth = <128>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x>;
> > + status = "disabled";
> > + };
> > +
> > rst: rstmgr@ffd11000 {
> > #reset-cells = <1>;
> > compatible = "altr,rst-mgr";
> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > new file mode 100755
> > index 000..e1cfb522bfc
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> > @@ -0,0 +1,25 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot additions
> > + *
> > + * Copyright (C) 2019 Intel Corporation
> > + */
> > +
> > +/{
> > + aliases {
> > + spi0 =
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > + {
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <1>;
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + u-boot,dm-pre-reloc;
> > +};
> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> > b/arch/arm/dts/socfpga_stratix10_socdk.dts
> > old mode 100644
> > new mode 100755
> > index 6e8ddcd9f4c..09c8a174671
> > --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> > @@ -85,6 +85,41 @@
> > smplsel = <0>;
> > };
> >
> > + {
> > + flash0: flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "n25q00a";
> > + reg = <0>;
> > + spi-max-frequency = <5000>;
> > +
> > + m25p,fast-read;
> > + cdns,page-size = <256>;
> > + cdns,block-size = <16>;
> > + cdns,read-delay = <1>;
> > + cdns,tshsl-ns = <50>;
> > + cdns,tsd2d-ns = <50>;
> > + cdns,tchsh-ns = <4>;
> > + cdns,tslch-ns = <4>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + qspi_boot: partition@0 {
> > + label = "Boot and fpga data";
> > + reg = <0x0 0x400>;
> > + };
> > +
> > + qspi_rootfs: partition@400 {
> > + label = "Root Filesystem - JFFS2";
> > +
Re: [U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node
On Wed, Apr 3, 2019 at 1:45 PM Ley Foon Tan wrote:
>
> Merge qspi dts node from Linux.
> Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)
>
> Add -u-boot.dtsi files for non Linux dts properties and
> update properties for Uboot.
> - add u-boot,dm-pre-reloc
> - add alias for spi0
> - change compatible for flash
> - support quad read and quad write
> - change maximum frequency to 100MHz
>
> Tested on Stratix 10 SoC devkit.
> SOCFPGA_STRATIX10 # sf probe 0:0
> SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256
> MiB
>
> Signed-off-by: Ley Foon Tan
>
> ---
> v4->v5:
> - Add -u-boot.dtsi
> - Update commit message with Linux commit ID
>
> v3->v4:
> - Add qspi node to dtsi based on alphabetical order
> - Add spi-tx-bus-width and spi-rx-bus-width
>
> v2->v3:
> - Change flash compatible to "jedec,spi-nor"
> - Change spi-max-frequency to 100MHz
> ---
> arch/arm/dts/socfpga_stratix10.dtsi | 13 +++
> .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 25 +
> arch/arm/dts/socfpga_stratix10_socdk.dts | 35 +++
> 3 files changed, 73 insertions(+)
> mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi
> create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
> b/arch/arm/dts/socfpga_stratix10.dtsi
> old mode 100644
> new mode 100755
> index ee93725d648..d1ae2fabae0
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -237,6 +237,19 @@
> reg = <0xffe0 0x10>;
> };
>
> + qspi: spi@ff8d2000 {
> + compatible = "cdns,qspi-nor";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xff8d2000 0x100>,
> + <0xff90 0x10>;
> + interrupts = <0 3 4>;
> + cdns,fifo-depth = <128>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x>;
> + status = "disabled";
> + };
> +
> rst: rstmgr@ffd11000 {
> #reset-cells = <1>;
> compatible = "altr,rst-mgr";
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> new file mode 100755
> index 000..e1cfb522bfc
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2019 Intel Corporation
> + */
> +
> +/{
> + aliases {
> + spi0 =
> + };
> +};
> +
> + {
> + status = "okay";
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <1>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> old mode 100644
> new mode 100755
> index 6e8ddcd9f4c..09c8a174671
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -85,6 +85,41 @@
> smplsel = <0>;
> };
>
> + {
> + flash0: flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "n25q00a";
> + reg = <0>;
> + spi-max-frequency = <5000>;
> +
> + m25p,fast-read;
> + cdns,page-size = <256>;
> + cdns,block-size = <16>;
> + cdns,read-delay = <1>;
> + cdns,tshsl-ns = <50>;
> + cdns,tsd2d-ns = <50>;
> + cdns,tchsh-ns = <4>;
> + cdns,tslch-ns = <4>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qspi_boot: partition@0 {
> + label = "Boot and fpga data";
> + reg = <0x0 0x400>;
> + };
> +
> + qspi_rootfs: partition@400 {
> + label = "Root Filesystem - JFFS2";
> + reg = <0x400 0x400>;
> + };
> + };
> + };
> +};
> +
> {
> status = "okay";
> };
> --
Any further comment on this patch?
Regards
Ley Foon
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[U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node
Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)
Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz
Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256
MiB
Signed-off-by: Ley Foon Tan
---
v4->v5:
- Add -u-boot.dtsi
- Update commit message with Linux commit ID
v3->v4:
- Add qspi node to dtsi based on alphabetical order
- Add spi-tx-bus-width and spi-rx-bus-width
v2->v3:
- Change flash compatible to "jedec,spi-nor"
- Change spi-max-frequency to 100MHz
---
arch/arm/dts/socfpga_stratix10.dtsi | 13 +++
.../dts/socfpga_stratix10_socdk-u-boot.dtsi | 25 +
arch/arm/dts/socfpga_stratix10_socdk.dts | 35 +++
3 files changed, 73 insertions(+)
mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi
create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
old mode 100644
new mode 100755
index ee93725d648..d1ae2fabae0
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -237,6 +237,19 @@
reg = <0xffe0 0x10>;
};
+ qspi: spi@ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff90 0x10>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x>;
+ status = "disabled";
+ };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
new file mode 100755
index 000..e1cfb522bfc
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation
+ */
+
+/{
+ aliases {
+ spi0 =
+ };
+};
+
+ {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
old mode 100644
new mode 100755
index 6e8ddcd9f4c..09c8a174671
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -85,6 +85,41 @@
smplsel = <0>;
};
+ {
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00a";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x400>;
+ };
+
+ qspi_rootfs: partition@400 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x400 0x400>;
+ };
+ };
+ };
+};
+
{
status = "okay";
};
--
2.19.0
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