On 08/10/2017 10:39 PM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
>
> This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
> mov
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and
moves existing register space definaton of CCI-400 bus
from
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