Hi Andre,
On Thu, 19 Sep 2013 18:06:40 +0200, Andre Przywara
andre.przyw...@linaro.org wrote:
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following text
. I could be wrong here, just checking
B1.5.1 Arm Arch Ref Manual
-
To avoid security holes, software must not:
-
— Change from Secure to Non-secure state by using an MSR or CPS
instruction
to
On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following text
. I could be wrong here, just checking
In the future, if you can comment specifically inline on the lines of
code you are targeting, it is easier for other people
On Fri, Sep 20, 2013 at 6:12 AM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following
text
. I could be wrong here, just checking
In the future, if you can
On Fri, Sep 20, 2013 at 08:08:45AM +0530, Mj Embd wrote:
On Fri, Sep 20, 2013 at 6:12 AM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Fri, Sep 20, 2013 at 03:20:15AM +0530, Mj Embd wrote:
Just checking, is the mcr p15,0,r1,c1,c1,0 in sync with the following
text
. I could
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