Re: [U-Boot] [U-Boot PATCH 3/8] spi: Zap ftssp010_spi driver
Hi Axel, On 22 April 2015 at 06:09, Axel Lin axel@ingics.com wrote: 2015-04-22 2:26 GMT+08:00 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com: Zap ftssp010_spi driver since the boards used this driver is no longer been active. I'm not sure if this is correct thing to do... It's fine to drop unmaintained boards, but a driver can/may be used by different boards. So If someday the boards(or new boards) that need this driver becomes active, it needs to add back this(and all required) driver(s). I understand your point, but if none of the sw using these drivers will make orphan driver and to reduce the code size atleast some thing is not used now. Ok, if any boards require these may be they will write or reuse it from past that depends on the future decision. Any comments from ML? thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot PATCH 3/8] spi: Zap ftssp010_spi driver
Zap ftssp010_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Kuo-Jung Su dant...@faraday-tech.com
Cc: Axel Lin axel@ingics.com
---
drivers/spi/Makefile | 1 -
drivers/spi/ftssp010_spi.c | 498 -
2 files changed, 499 deletions(-)
delete mode 100644 drivers/spi/ftssp010_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 93065b7..1e3611d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
-obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
deleted file mode 100644
index c7d6480..000
--- a/drivers/spi/ftssp010_spi.c
+++ /dev/null
@@ -1,498 +0,0 @@
-/*
- * (C) Copyright 2013
- * Faraday Technology Corporation. http://www.faraday-tech.com/tw/
- * Kuo-Jung Su dant...@gmail.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include linux/compat.h
-#include asm/io.h
-#include malloc.h
-#include spi.h
-
-#ifndef CONFIG_FTSSP010_BASE_LIST
-#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_BASE
-#define CONFIG_FTSSP010_GPIO_BASE 0
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_LIST
-#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_CLOCK
-#define CONFIG_FTSSP010_CLOCK clk_get_rate(SSP);
-#endif
-
-#ifndef CONFIG_FTSSP010_TIMEOUT
-#define CONFIG_FTSSP010_TIMEOUT 100
-#endif
-
-/* FTSSP010 chip registers */
-struct ftssp010_regs {
- uint32_t cr[3];/* control register */
- uint32_t sr; /* status register */
- uint32_t icr; /* interrupt control register */
- uint32_t isr; /* interrupt status register */
- uint32_t dr; /* data register */
- uint32_t rsvd[17];
- uint32_t revr; /* revision register */
- uint32_t fear; /* feature register */
-};
-
-/* Control Register 0 */
-#define CR0_FFMT_MASK (7 12)
-#define CR0_FFMT_SSP(0 12)
-#define CR0_FFMT_SPI(1 12)
-#define CR0_FFMT_MICROWIRE (2 12)
-#define CR0_FFMT_I2S(3 12)
-#define CR0_FFMT_AC97 (4 12)
-#define CR0_FLASH (1 11)
-#define CR0_FSDIST(x) (((x) 0x03) 8)
-#define CR0_LOOP(1 7) /* loopback mode */
-#define CR0_LSB (1 6) /* LSB */
-#define CR0_FSPO(1 5) /* fs atcive low (I2S only) */
-#define CR0_FSJUSTIFY (1 4)
-#define CR0_OPM_SLAVE (0 2)
-#define CR0_OPM_MASTER (3 2)
-#define CR0_OPM_I2S_MSST(3 2) /* master stereo mode */
-#define CR0_OPM_I2S_MSMO(2 2) /* master mono mode */
-#define CR0_OPM_I2S_SLST(1 2) /* slave stereo mode */
-#define CR0_OPM_I2S_SLMO(0 2) /* slave mono mode */
-#define CR0_SCLKPO (1 1) /* clock polarity */
-#define CR0_SCLKPH (1 0) /* clock phase */
-
-/* Control Register 1 */
-#define CR1_PDL(x) (((x) 0xff) 24) /* padding length */
-#define CR1_SDL(x) x) - 1) 0x1f) 16) /* data length */
-#define CR1_DIV(x) (((x) - 1) 0x) /* clock divider */
-
-/* Control Register 2 */
-#define CR2_CS(x)(((x) 3) 10) /* CS/FS select */
-#define CR2_FS (1 9) /* CS/FS signal level */
-#define CR2_TXEN (1 8) /* tx enable */
-#define CR2_RXEN (1 7) /* rx enable */
-#define CR2_RESET(1 6) /* chip reset */
-#define CR2_TXFC (1 3) /* tx fifo Clear */
-#define CR2_RXFC (1 2) /* rx fifo Clear */
-#define CR2_TXDOE(1 1) /* tx data output enable */
-#define CR2_EN (1 0) /* chip enable */
-
-/* Status Register */
-#define SR_RFF (1 0) /* rx fifo full */
-#define SR_TFNF (1 1) /* tx fifo not full */
-#define SR_BUSY (1 2) /* chip busy */
-#define SR_RFVE(reg) (((reg) 4) 0x1f) /* rx fifo valid entries */
-#define SR_TFVE(reg) (((reg) 12) 0x1f) /* tx fifo valid entries */
-
-/* Feature Register */
-#define FEAR_BITS(reg) reg) 0) 0xff) + 1) /* data width */
-#define FEAR_RFSZ(reg) reg) 8) 0xff) + 1) /* rx fifo size */
-#define FEAR_TFSZ(reg) reg) 16) 0xff) + 1) /* tx fifo size */
-#define FEAR_AC97(1 24)
-#define FEAR_I2S (1 25)
-#define FEAR_SPI_MWR (1 26)
-#define FEAR_SSP (1 27)
-#define FEAR_SPDIF (1 28)
-
-/* FTGPIO010 chip registers */
-struct ftgpio010_regs {
- uint32_t out; /* 0x00: Data Output */
- uint32_t in; /* 0x04: Data Input */
- uint32_t dir; /* 0x08: Direction */
- uint32_t bypass; /* 0x0c: Bypass */
- uint32_t set; /* 0x10: Data Set */
- uint32_t clr;
Re: [U-Boot] [U-Boot PATCH 3/8] spi: Zap ftssp010_spi driver
2015-04-22 2:26 GMT+08:00 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com: Zap ftssp010_spi driver since the boards used this driver is no longer been active. I'm not sure if this is correct thing to do... It's fine to drop unmaintained boards, but a driver can/may be used by different boards. So If someday the boards(or new boards) that need this driver becomes active, it needs to add back this(and all required) driver(s). Regards, Axel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
