+ Vasily
On Tue, May 8, 2018 at 6:45 PM, Andre Przywara wrote:
> Hi,
>
> On 08/05/18 11:34, Jagan Teki wrote:
>> On Sun, Apr 1, 2018 at 8:11 AM, Chen-Yu Tsai wrote:
>>> On Sun, Apr 1, 2018 at 9:28 AM, André Przywara
>>> wrote:
On 30/03/18 05:25, Chen-Yu Tsai wrote:
>>
Hi,
On 08/05/18 11:34, Jagan Teki wrote:
> On Sun, Apr 1, 2018 at 8:11 AM, Chen-Yu Tsai wrote:
>> On Sun, Apr 1, 2018 at 9:28 AM, André Przywara
>> wrote:
>>> On 30/03/18 05:25, Chen-Yu Tsai wrote:
>>>
>>>
> OK. So meanwhile I have something
On Sun, Apr 1, 2018 at 8:11 AM, Chen-Yu Tsai wrote:
> On Sun, Apr 1, 2018 at 9:28 AM, André Przywara wrote:
>> On 30/03/18 05:25, Chen-Yu Tsai wrote:
>>
>>
OK. So meanwhile I have something almost(TM) working:
- drivers/clk/sunxi/clk-a64.c,
On Sun, Apr 1, 2018 at 9:28 AM, André Przywara wrote:
> On 30/03/18 05:25, Chen-Yu Tsai wrote:
>
>
>>> OK. So meanwhile I have something almost(TM) working:
>>> - drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
>>> the clock IDs from
On 30/03/18 05:25, Chen-Yu Tsai wrote:
>> OK. So meanwhile I have something almost(TM) working:
>> - drivers/clk/sunxi/clk-a64.c, which is a UCLASS_CLK implementation of
>> the clock IDs from allwinner,sun50i-a64-ccu that we need: CLK_BUS_UARTx,
>> CLK_BUS_MMCx, CLK_MMCx. Their
Hi,
On Tue, Mar 27, 2018 at 10:43 PM, Andre Przywara wrote:
> Hi Maxime,
>
> thanks for the answer.
>
> On 27/03/18 15:30, Maxime Ripard wrote:
>> Hi,
>>
>> On Sat, Mar 24, 2018 at 01:07:27AM +, André Przywara wrote:
>>> On 23/03/18 18:14, Jagan Teki wrote:
On
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