Re: [U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
> -Original Message-
> From: Lukasz Majewski
> Sent: 2019年5月29日 14:40
> To: Y.b. Lu
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> Subject: Re: [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
>
> On Tue, 21 May 2019 08:52:44 +
> "Y.b. Lu" wrote:
>
> > Dropped i.MX code which couldn't be reused.
> >
> > Signed-off-by: Yangbo Lu
> > ---
> > Changes for v2:
> > - Added this patch.
> > Changes for v3:
> > - Rebased.
> > ---
> > drivers/mmc/fsl_esdhc.c | 609
> > ++-- include/fsl_esdhc.h |
> > 57 2 files changed, 21 insertions(+), 645 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 1b7de74a72..3f4f75ae4c 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -16,14 +16,11 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include
> > #include
> > #include
> > -#include
> > -#include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> > IRQSTATEN_CIE | IRQSTATEN_DTOE |
> > IRQSTATEN_DCE | \ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
> | \
> > IRQSTATEN_DINT)
> > -#define MAX_TUNING_LOOP 40
> > -
> > struct fsl_esdhc {
> > uintdsaddr; /* SDMA system address
> > register */ uintblkattr;/* Block attributes register */
> > @@ -54,37 +49,20 @@ struct fsl_esdhc {
> > uintautoc12err; /* Auto CMD error status register
> > */ uinthostcapblt; /* Host controller capabilities
> > register */ uintwml;/* Watermark level register */
> > - uintmixctrl;/* For USDHC */
> > - charreserved1[4]; /* reserved */
> > + charreserved1[8]; /* reserved */
> > uintfevt; /* Force event register */
> > uintadmaes; /* ADMA error status register
> > */ uintadsaddr; /* ADMA system address register */
> > - charreserved2[4];
> > - uintdllctrl;
> > - uintdllstat;
> > - uintclktunectrlstatus;
> > - charreserved3[4];
> > - uintstrobe_dllctrl;
> > - uintstrobe_dllstat;
> > - charreserved4[72];
> > - uintvendorspec;
> > - uintmmcboot;
> > - uintvendorspec2;
> > - uinttuning_ctrl;/* on i.MX6/7/8 */
> > - charreserved5[44];
> > + charreserved2[160];
> > uinthostver;/* Host controller version register
> > */
> > - charreserved6[4]; /* reserved */
> > + charreserved3[4]; /* reserved */
> > uintdmaerraddr; /* DMA error address register */
> > - charreserved7[4]; /* reserved */
> > + charreserved4[4]; /* reserved */
> > uintdmaerrattr; /* DMA error attribute register */
> > - charreserved8[4]; /* reserved */
> > + charreserved5[4]; /* reserved */
> > uinthostcapblt2;/* Host controller capabilities
> > register 2 */
> > - charreserved9[8]; /* reserved */
> > - uinttcr;/* Tuning control register */
> > - charreserved10[28]; /* reserved */
> > - uintsddirctl; /* SD direction control register */
> > - charreserved11[712];/* reserved */
> > - uintscr;/* eSDHC control register */
> > + charreserved6[756]; /* reserved */
> > + uintesdhcctl; /* eSDHC control register */
> > };
> >
> > struct fsl_esdhc_plat {
> > @@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
> > struct mmc mmc;
> > };
> >
> > -struct esdhc_soc_data {
> > - u32 flags;
> > - u32 caps;
> > -};
> > -
> > /**
> > * struct fsl_esdhc_priv
> > *
> > @@ -109,13 +82,6 @@ struct esdhc_soc_data {
> > * @dev: pointer for the device
> > * @non_removable: 0: removable; 1: non-removable
> > * @wp_enable: 1: enable checking wp; 0: no check
>
Re: [U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
On Tue, 21 May 2019 08:52:44 +
"Y.b. Lu" wrote:
> Dropped i.MX code which couldn't be reused.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v2:
> - Added this patch.
> Changes for v3:
> - Rebased.
> ---
> drivers/mmc/fsl_esdhc.c | 609
> ++-- include/fsl_esdhc.h |
> 57 2 files changed, 21 insertions(+), 645 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 1b7de74a72..3f4f75ae4c 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -16,14 +16,11 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> #include
> #include
> -#include
> -#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> IRQSTATEN_CIE | IRQSTATEN_DTOE |
> IRQSTATEN_DCE | \ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
> IRQSTATEN_DINT)
> -#define MAX_TUNING_LOOP 40
> -
> struct fsl_esdhc {
> uintdsaddr; /* SDMA system address
> register */ uintblkattr; /* Block attributes register */
> @@ -54,37 +49,20 @@ struct fsl_esdhc {
> uintautoc12err; /* Auto CMD error status register
> */ uinthostcapblt;/* Host controller capabilities
> register */ uintwml; /* Watermark level register */
> - uintmixctrl;/* For USDHC */
> - charreserved1[4]; /* reserved */
> + charreserved1[8]; /* reserved */
> uintfevt; /* Force event register */
> uintadmaes; /* ADMA error status register
> */ uintadsaddr; /* ADMA system address register */
> - charreserved2[4];
> - uintdllctrl;
> - uintdllstat;
> - uintclktunectrlstatus;
> - charreserved3[4];
> - uintstrobe_dllctrl;
> - uintstrobe_dllstat;
> - charreserved4[72];
> - uintvendorspec;
> - uintmmcboot;
> - uintvendorspec2;
> - uinttuning_ctrl;/* on i.MX6/7/8 */
> - charreserved5[44];
> + charreserved2[160];
> uinthostver;/* Host controller version register
> */
> - charreserved6[4]; /* reserved */
> + charreserved3[4]; /* reserved */
> uintdmaerraddr; /* DMA error address register */
> - charreserved7[4]; /* reserved */
> + charreserved4[4]; /* reserved */
> uintdmaerrattr; /* DMA error attribute register */
> - charreserved8[4]; /* reserved */
> + charreserved5[4]; /* reserved */
> uinthostcapblt2;/* Host controller capabilities
> register 2 */
> - charreserved9[8]; /* reserved */
> - uinttcr;/* Tuning control register */
> - charreserved10[28]; /* reserved */
> - uintsddirctl; /* SD direction control register */
> - charreserved11[712];/* reserved */
> - uintscr;/* eSDHC control register */
> + charreserved6[756]; /* reserved */
> + uintesdhcctl; /* eSDHC control register */
> };
>
> struct fsl_esdhc_plat {
> @@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
> struct mmc mmc;
> };
>
> -struct esdhc_soc_data {
> - u32 flags;
> - u32 caps;
> -};
> -
> /**
> * struct fsl_esdhc_priv
> *
> @@ -109,13 +82,6 @@ struct esdhc_soc_data {
> * @dev: pointer for the device
> * @non_removable: 0: removable; 1: non-removable
> * @wp_enable: 1: enable checking wp; 0: no check
> - * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
> - * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
> - * @caps: controller capabilities
> - * @tuning_step: tuning step setting in tuning_ctrl register
> - * @start_tuning_tap: the start point for tuning in tuning_ctrl
> register
> - * @strobe_dll_delay_target: settings in strobe_dllctrl
> - * @signal_voltage: indicating the current voltage
> * @cd_gpio: gpio for card detection
> * @wp_gpio: gpio for write protection
> */
> @@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
> unsigned int sdhc_clk;
> struct clk per_clk;
> unsigned int clock;
> - unsigned int mode;
> unsigned int bus_width;
> #if !CONFIG_IS_ENABLED(BLK)
> struct mmc *mmc;
> @@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
> struct udevice *dev;
> int non_removable;
> int wp_enable;
> - int vs18_enable;
> - u32 flags;
> - u32 caps;
> - u32 tuning_step;
> - u32 tuning_start_tap;
> - u32 strobe_dll_delay_target;
> - u32 signal_voltage;
> -#if IS_ENABLED(CONFIG_DM_REGULATOR)
> - struct udevice *vqmmc_dev;
> - struct udevice *vmmc_dev;
> -#endif
> -#ifdef CONFIG_DM_GPIO
> - struct gpio_desc cd_gpio;
> - struct gpio_desc wp_gpio;
> -#endif
I suppose that _all_ 85xx and layerscape/OorIQ boards are not converted
to DM and they are not using card detect and write protect pins?
IIRC the
Re: [U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
> Subject: [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
>
> Dropped i.MX code which couldn't be reused.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v2:
> - Added this patch.
> Changes for v3:
> - Rebased.
> ---
> drivers/mmc/fsl_esdhc.c | 609 ++--
> include/fsl_esdhc.h | 57
> 2 files changed, 21 insertions(+), 645 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> 1b7de74a72..3f4f75ae4c 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -16,14 +16,11 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> #include
> #include
> -#include
> -#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE
> | \
> IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR |
> \
> IRQSTATEN_DINT)
> -#define MAX_TUNING_LOOP 40
> -
> struct fsl_esdhc {
> uintdsaddr; /* SDMA system address register */
> uintblkattr;/* Block attributes register */
> @@ -54,37 +49,20 @@ struct fsl_esdhc {
> uintautoc12err; /* Auto CMD error status register */
> uinthostcapblt; /* Host controller capabilities register */
> uintwml;/* Watermark level register */
> - uintmixctrl;/* For USDHC */
> - charreserved1[4]; /* reserved */
> + charreserved1[8]; /* reserved */
> uintfevt; /* Force event register */
> uintadmaes; /* ADMA error status register */
> uintadsaddr;/* ADMA system address register */
> - charreserved2[4];
> - uintdllctrl;
> - uintdllstat;
> - uintclktunectrlstatus;
> - charreserved3[4];
> - uintstrobe_dllctrl;
> - uintstrobe_dllstat;
> - charreserved4[72];
> - uintvendorspec;
> - uintmmcboot;
> - uintvendorspec2;
> - uinttuning_ctrl;/* on i.MX6/7/8 */
> - charreserved5[44];
> + charreserved2[160];
> uinthostver;/* Host controller version register */
> - charreserved6[4]; /* reserved */
> + charreserved3[4]; /* reserved */
> uintdmaerraddr; /* DMA error address register */
> - charreserved7[4]; /* reserved */
> + charreserved4[4]; /* reserved */
> uintdmaerrattr; /* DMA error attribute register */
> - charreserved8[4]; /* reserved */
> + charreserved5[4]; /* reserved */
> uinthostcapblt2;/* Host controller capabilities register 2 */
> - charreserved9[8]; /* reserved */
> - uinttcr;/* Tuning control register */
> - charreserved10[28]; /* reserved */
> - uintsddirctl; /* SD direction control register */
> - charreserved11[712];/* reserved */
> - uintscr;/* eSDHC control register */
> + charreserved6[756]; /* reserved */
> + uintesdhcctl; /* eSDHC control register */
> };
>
> struct fsl_esdhc_plat {
> @@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
> struct mmc mmc;
> };
>
> -struct esdhc_soc_data {
> - u32 flags;
> - u32 caps;
> -};
> -
> /**
> * struct fsl_esdhc_priv
> *
> @@ -109,13 +82,6 @@ struct esdhc_soc_data {
> * @dev: pointer for the device
> * @non_removable: 0: removable; 1: non-removable
> * @wp_enable: 1: enable checking wp; 0: no check
> - * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
> - * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
> - * @caps: controller capabilities
> - * @tuning_step: tuning step setting in tuning_ctrl register
> - * @start_tuning_tap: the start point for tuning in tuning_ctrl register
> - * @strobe_dll_delay_target: settings in strobe_dllctrl
> - * @signal_voltage: indicating the current voltage
> * @cd_gpio: gpio for card detection
> * @wp_gpio: gpio for write protection
> */
> @@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
> unsigned int sdhc_clk;
> struct clk per_clk;
> unsigned int clock;
> - unsigned int mode;
> unsigned int bus_width;
> #if !CONFIG_IS_ENABLED(BLK)
> struct mmc *mmc;
> @@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
> struct udevice *dev;
> int non_removable;
> int wp_enable;
> - int vs18_enable;
> - u32 flags;
> - u32 caps;
> - u32 tuning_step;
> - u32 tuning_start_tap;
> - u32 strobe_dll_delay_target;
> - u32 signal_voltage;
> -#if IS_ENABLED(CONFIG_DM_REGULATOR)
> - struct udevice *vqmmc_dev;
> - struct udevice *vmmc_dev;
> -#endif
> -#ifdef CONFIG_DM_GPIO
> - struct gpio_desc cd_gpio;
> - struct gpio_desc wp_gpio;
> -#endif
> };
>
> /* Return the XFERTYP flags for a given command and data packet */ @@
>
[U-Boot] [v3, 4/5] mmc: fsl_esdhc: drop i.MX code
Dropped i.MX code which couldn't be reused.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Added this patch.
Changes for v3:
- Rebased.
---
drivers/mmc/fsl_esdhc.c | 609 ++--
include/fsl_esdhc.h | 57
2 files changed, 21 insertions(+), 645 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1b7de74a72..3f4f75ae4c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -16,14 +16,11 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
-#include
-#include
DECLARE_GLOBAL_DATA_PTR;
@@ -33,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE
| \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR
| \
IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
-
struct fsl_esdhc {
uintdsaddr; /* SDMA system address register */
uintblkattr;/* Block attributes register */
@@ -54,37 +49,20 @@ struct fsl_esdhc {
uintautoc12err; /* Auto CMD error status register */
uinthostcapblt; /* Host controller capabilities register */
uintwml;/* Watermark level register */
- uintmixctrl;/* For USDHC */
- charreserved1[4]; /* reserved */
+ charreserved1[8]; /* reserved */
uintfevt; /* Force event register */
uintadmaes; /* ADMA error status register */
uintadsaddr;/* ADMA system address register */
- charreserved2[4];
- uintdllctrl;
- uintdllstat;
- uintclktunectrlstatus;
- charreserved3[4];
- uintstrobe_dllctrl;
- uintstrobe_dllstat;
- charreserved4[72];
- uintvendorspec;
- uintmmcboot;
- uintvendorspec2;
- uinttuning_ctrl;/* on i.MX6/7/8 */
- charreserved5[44];
+ charreserved2[160];
uinthostver;/* Host controller version register */
- charreserved6[4]; /* reserved */
+ charreserved3[4]; /* reserved */
uintdmaerraddr; /* DMA error address register */
- charreserved7[4]; /* reserved */
+ charreserved4[4]; /* reserved */
uintdmaerrattr; /* DMA error attribute register */
- charreserved8[4]; /* reserved */
+ charreserved5[4]; /* reserved */
uinthostcapblt2;/* Host controller capabilities register 2 */
- charreserved9[8]; /* reserved */
- uinttcr;/* Tuning control register */
- charreserved10[28]; /* reserved */
- uintsddirctl; /* SD direction control register */
- charreserved11[712];/* reserved */
- uintscr;/* eSDHC control register */
+ charreserved6[756]; /* reserved */
+ uintesdhcctl; /* eSDHC control register */
};
struct fsl_esdhc_plat {
@@ -92,11 +70,6 @@ struct fsl_esdhc_plat {
struct mmc mmc;
};
-struct esdhc_soc_data {
- u32 flags;
- u32 caps;
-};
-
/**
* struct fsl_esdhc_priv
*
@@ -109,13 +82,6 @@ struct esdhc_soc_data {
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
* @cd_gpio: gpio for card detection
* @wp_gpio: gpio for write protection
*/
@@ -124,7 +90,6 @@ struct fsl_esdhc_priv {
unsigned int sdhc_clk;
struct clk per_clk;
unsigned int clock;
- unsigned int mode;
unsigned int bus_width;
#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
@@ -132,21 +97,6 @@ struct fsl_esdhc_priv {
struct udevice *dev;
int non_removable;
int wp_enable;
- int vs18_enable;
- u32 flags;
- u32 caps;
- u32 tuning_step;
- u32 tuning_start_tap;
- u32 strobe_dll_delay_target;
- u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
- struct udevice *vqmmc_dev;
- struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
- struct gpio_desc cd_gpio;
- struct gpio_desc wp_gpio;
-#endif
};
/* Return the XFERTYP flags for a given command and data packet */
@@ -258,8 +208,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv,
struct mmc *mmc,
{
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE)
