Hi Bin,
To avoid top-posting I will send another email.
Basically my Broadwell-DE implementation work, on both Camelback mountain CRB
(DIMM memory) and our custom design product (memory down). I can't submit the
patch to U-Boot because in both cases the booting process takes 1 hour and 20
minutes and there are no errors in the log. The platform takes lot of time to
boot when it reach "DDRIO Initialization".
I have attached the boot log if it may help, and my source-code is available
here: https://github.com/WarOfDevil/u-boot.x86_64-broadwell-de
Thanks in advance!
Vincenzo
Sent with [ProtonMail](https://protonmail.com) Secure Email.
============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.2) =============
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0
Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6D4
Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A
Loading PEIM at 0x000FFEBCA2C EntryPoint=0x000FFEBD000
enable all DMI VCx
:: CPU Type Socket ModelId# 56
:: CPU stepping # 1
Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B
Publish PlatformInfoPPI
Loading PEIM at 0x000FFEBE6BC EntryPoint=0x000FFEBEC24
Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF
ME PEI Platform Policy PPI Installed
Loading PEIM at 0x000FFEBFBEC EntryPoint=0x000FFEC04F8
Force an S5 exit path.
Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8
Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74
Loading PEIM at 0x000FFEC247C EntryPoint=0x000FFEC33E4
Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1
ME UMA: ME UMA PPI Installed
Loading PEIM at 0x000FFEC5064 EntryPoint=0x000FFEC5CD4
[SPS] Waiting for ME firmware init complete
[SPS] WARNING: ME is in recovery mode (cause: 3)
[HECI-0] VID-DID: 8086-8C3A
[HECI-0] MBAR not programmed, using default 0x00000000FEDB0000
[SPS] Sending ME-BIOS Interface Version request
[HECI-0] Send msg: 80010020
[HECI-0] Got msg: 80050020
[SPS] SPS ME-BIOS interface version is 1.0
Feature set is 0x0000
[SPS] HOB: features 0x00, flow 1, boot mode 0, cores to disable 0
Loading PEIM at 0x000FFEC7B2C EntryPoint=0x000FFEF4044
OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD
upd->MemDdr4Platform = 0x0
tsc->DDR4Platform = 0x2
Halting the TCO Timer (Watchdog)
FastBoot is not supported on this SKU.
Running on hardware
Revision: 0
BIOSSIM: InitHeap()
BIOSSIM: InitUSBDebug()
BDX (1HA) processor detected
CPU Stepping 1
Found
CCMRC Version: 00500000
MRC Sync Number: 244071
RC Version: 02000000
host = FE191770 (pointer to sysHost structure)
Legacy Serial Debug Enabled
QPI Init starting...
******* QPI Setup Structure *******
PPINrOptIn: 0
Bus Ratio: 1 1 1 1
IO Ratio: 1 1 1 1
MMIOL Ratio: 1 1 1 1
LegacyVgaSoc: 0
MmioP2pDis: 0
IsocAzaliaVc1En: 0
DebugPrintLevel: 15
ClusterOnDieEn: 0
IBPECIEn: 1
E2EParityEn: 0
EarlySnoopEn: 1
HomeDirWOSBEn: 1
DegradePrecedence: 0
QpiLinkSpeedMode: 1 (FAST)
QpiLinkSpeed: 6
QpiLinkL0pEn: 1
QpiLinkL1En: 1
QpiLinkL0rEn: 1
QpiLbEn: 0
IioUniphyDisable (per socket): 0 0 0 0
QpiLinkCreditReduce: 2
QpiConfigTxWci: 11
QpiCrcMode: 0
QpiCpuSktHotPlugEn: 0
QpiCpuSktHotPlugTopology: 0
QpiSkuMismatchCheck: 1
QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6
QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11
Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
******* Common Setup Structure *******
mmCfgBase: 0x80000000
mmCfgSize: 0x10000000
mmiolBase: 0x90000000
mmiolSize: 0x6C000000
mmiohBase: 0x00003800-00000000
mmiohSize: 256 GB
numaEn: 1
isocEn: 0
mesegEn: 0
dcaEn: 1
******* Common Var Structure *******
resetRequired: 0
state: 0
numCpus: 0
socketPresentBitMap: 0x01
busIio: 0x00 0x00 0x00 0x00
busUncore: 0x3F 0x00 0x00 0x00
mmCfgBase: 0x80000000
;******* Collecting Early System Information - START *******
CAPID0[5] is set. SKU Detected as DE.
SocketId: 0 Physical Chop: 3
SocketId: 0 CAPID5: 0x06000B6D
SocketId: 0 CAPID4: 0x24080F02
SocketId: 0 CAPID3: 0x009B0220
SocketId: 0 CAPID2: 0x53B40000
SocketId: 0 CAPID1: 0x8C000083
SocketId: 0 CAPID0: 0x00108120
; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x01 CAPID4[sbsp]:
0x24080F02
; Total Cbos: 08 Cbo List: 0xB6D Total HA: 01 Total R3Qpi: 00 Total
QpiAgent: 00
; TotCpus: 4 CpuList: 0x0F
; busIio: 0x00 0x40 0x80 0xC0
; busUncore: 0x3F 0x7F 0xBF 0xFF
; Reset Type: Cold Reset Link Speed: Slow Speed
;******* Collecting Early System Information - END *******
;******* Setting up Minimum Path - START *******
; Constructing SBSP minimum path Topology Tree
; --------------------------------------------
; Adding SBSP (CPU0) to the tree
CPU0 Link Exchange
UseQpiPcSts = 1
;SBSP Minimum Path Tree
;----------------------
;Index Socket ParentPort Hop ParentIndex
; 00 CPU0 -- 0 --
;******* Setting up Minimum Path - END *******
;******* Initialize MCTP - START *******
;******* Initialize MCTP - END *******
;******* Check for QPI Topology Degradation - START *******
;Link Exchange Parameter
;-----------------------
;CPU0
; Already Reduced to Supported Topology
; System will be treated 1S Configuration
;******* Check for QPI Topology Degradation - END *******
;******* Checking QPIRC Input Structure - START *******
; Sys configuration Type = 16
;******* Checking QPIRC Input Structure - END *******
;******* Allocate RTIDs - START *******
; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 15 Extra - 06
; Local Base - 01 Reallocation Base - 65
; Cbo 04 RTID straddles into xRTID space
; RTIDs split into three pools of size 3, 8 and 4
; Sufficient extra RTIDs are available to move all the RTIDs into xRTID
space. No loss of RTIDs for the CBo.
; RTID Allocation Table
; ---------------------
; Local
; -----
; WB 0 1
; UBOX 0 0
; ISOC 1 0
; CBO00 1 8
; CBO00 9 7
; CBO01 16 8
; CBO01 24 7
; CBO02 31 8
; CBO02 39 7
; CBO03 46 8
; CBO03 54 7
; CBO04 65 8
; CBO04 73 7
; CBO05 80 8
; CBO05 88 7
; CBO06 95 8
; CBO06 103 7
; CBO07 110 8
; CBO07 118 7
; EXTRA 0 3
;******* Allocate RTIDs - END *******
;******* Cacluate Resource Allocation - START *******
;CPU Resource Allocation
;-----------------------
;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF
MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF
;******* Cacluate Resource Allocation - END *******
;******* Programming RTIDs and other Credits - START *******
;******* Programming RTIDs and other Credits - END *******
;******* Sync Up PBSPs - START *******
; Setting Ubox Sticky SR07 to 0x00000000
; Setting Ubox Sticky SR03 to 0x20000007
; Setting Ubox Sticky SR02 to 0x00000001
; Verifying if the remote socket(s) checked-in.
;******* Sync Up PBSPs - END *******
;******* Programming MSR for w/a - START *******
;******* Programming MSR for w/a - END *******
;******* Programming BGF Overrides - START *******
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x0
; Send Pcode mailbox command. Socket = 0 Command sent == 0x7D
; Wait for mailbox ready
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x11
; Send Pcode mailbox command. Socket = 0 Command sent == 0x17D
; Wait for mailbox ready
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x0
; Send Pcode mailbox command. Socket = 0 Command sent == 0x27D
; Wait for mailbox ready
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x0
; Send Pcode mailbox command. Socket = 0 Command sent == 0x37D
; Wait for mailbox ready
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x0
; Send Pcode mailbox command. Socket = 0 Command sent == 0x47D
; Wait for mailbox ready
;******* Programming BGF Overrides - END *******
;******* Full Speed Transition - START *******
; ;Single Socket, no QPI Links to transition
; Force unused links to disabled/low power state.
; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF
Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF
; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF
Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF
;******* Full Speed Transition - END *******
;******* Cod Activate - START *******
;******* Cod Activate - END *******
******* QPI Output Structure *******
OutLegacyVgaSoc: 0
OutIsocEn: 0
OutMesegEn: 0
OutIsocAzaliaVc1En: 0
OutClusterOnDieEn: 0
OutIBPECIEn: 1
OutE2EParityEn: 0
OutEarlySnoopEn: 1
OutHomeDirWOSBEn: 0
QpiCurrentLinkSpeedMode: 0 (SLOW)
OutQpiLinkSpeed: 6
OutQpiLinkL0pEn: 1
OutQpiLinkL1En: 1
OutQpiLinkL0rEn: 1
OutIioUniphyDisable: 0, 0, 0, 0
OutQpiCrcMode: 0
OutClusterOnDieReduction: 0
OutPointerSeperationHA: 0
QpiInternalGlobal->BtModeEn: 0
QpiInternalGlobal->BtMode: 0
QpiInternalGlobal->BtMode2Alt: 0
QpiInternalGlobal->Sys4SClusterOnDieEn: 0
QpiInternalGlobal->SnoopFanoutEn: 0
QpiInternalGlobal->SysSnoopMode: 0
QpiInternalGlobal->IodcEn: 0
;******* QPIRC Exit *******
QPI Init completed! Reset Requested: 2
Pipe Init starting...Pipe Init completed! Reset Requested: 2
CPU Feature Early Config starting...
CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset
Requested: 2
START_MRC_RUN
ME UMA: ME UMA Size Requested: 0
ME UMA size = 0 MBytes
forceColdBoot bit set
Get socket PPIN
Socket not PPIN Capable
setupChanged: 1
Clearing the MRC NVRAM structure.
bootMode = NormalBoot
subBootMode = ColdBoot
Dispatch Slaves -- Started
Dispatch Slaves - 0ms
Promote Warning Exception List -- Started
Promote Warning Exception List - 3ms
Initialize Throttling Early -- Started
Initialize Throttling Early - 150ms
Detect DIMM Configuration -- Started
Detect DIMM Configuration - 838ms
Get Slave Data -- Started
Get Slave Data - 2ms
Check POR Compatibility -- Started
RDIMM population
Check POR Compatibility - 20ms
Initialize DDR Clocks -- Started
GetPORDDRFreq returns ddrfreq = 10
Reset requested: non-MRC
MRC reset request!
Current DCLK: 12
Desired DCLK: 16, req_type = 0
Initialize DDR Clocks - 107ms
Send Status -- Started
Send Status -- EXIT, status = 2h
Total MRC time = 1467ms
Setting Last Boot Date = 6245 days
STOP_MRC_RUN
Reset Requested: 2
Pipe Exit starting...Pipe Exit completed! Reset Requested: 2
Checking for Reset Requests ...
Send HostResetWarning notification to ME.
ME UMA: WARNING: HostResetWarning called on non S3/4 resume flow (0) - ignored
HostResetWarning notification Complete.
Issue WARM RESET!
BIOS done set
============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.2) =============
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0
Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6D4
Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A
Loading PEIM at 0x000FFEBCA2C EntryPoint=0x000FFEBD000
enable all DMI VCx
:: CPU Type Socket ModelId# 56
:: CPU stepping # 1
Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B
Publish PlatformInfoPPI
Loading PEIM at 0x000FFEBE6BC EntryPoint=0x000FFEBEC24
Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF
ME PEI Platform Policy PPI Installed
Loading PEIM at 0x000FFEBFBEC EntryPoint=0x000FFEC04F8
Force an S5 exit path.
Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8
Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74
Loading PEIM at 0x000FFEC247C EntryPoint=0x000FFEC33E4
Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1
ME UMA: ME UMA PPI Installed
Loading PEIM at 0x000FFEC5064 EntryPoint=0x000FFEC5CD4
[SPS] Waiting for ME firmware init complete
[SPS] WARNING: ME is in recovery mode (cause: 3)
[HECI-0] VID-DID: 8086-8C3A
[HECI-0] MBAR not programmed, using default 0x00000000FEDB0000
[SPS] Sending ME-BIOS Interface Version request
[HECI-0] Send msg: 80010020
[HECI-0] Got msg: 80050020
[SPS] SPS ME-BIOS interface version is 1.0
Feature set is 0x0000
[SPS] HOB: features 0x00, flow 1, boot mode 0, cores to disable 0
Loading PEIM at 0x000FFEC7B2C EntryPoint=0x000FFEF4044
OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD
upd->MemDdr4Platform = 0x0
tsc->DDR4Platform = 0x2
Halting the TCO Timer (Watchdog)
FastBoot is not supported on this SKU.
Running on hardware
Revision: 0
BIOSSIM: InitHeap()
BIOSSIM: InitUSBDebug()
BDX (1HA) processor detected
CPU Stepping 1
Found
CCMRC Version: 00500000
MRC Sync Number: 244071
RC Version: 02000000
host = FE191770 (pointer to sysHost structure)
Legacy Serial Debug Enabled
QPI Init starting...
******* QPI Setup Structure *******
PPINrOptIn: 0
Bus Ratio: 1 1 1 1
IO Ratio: 1 1 1 1
MMIOL Ratio: 1 1 1 1
LegacyVgaSoc: 0
MmioP2pDis: 0
IsocAzaliaVc1En: 0
DebugPrintLevel: 15
ClusterOnDieEn: 0
IBPECIEn: 1
E2EParityEn: 0
EarlySnoopEn: 1
HomeDirWOSBEn: 1
DegradePrecedence: 0
QpiLinkSpeedMode: 1 (FAST)
QpiLinkSpeed: 6
QpiLinkL0pEn: 1
QpiLinkL1En: 1
QpiLinkL0rEn: 1
QpiLbEn: 0
IioUniphyDisable (per socket): 0 0 0 0
QpiLinkCreditReduce: 2
QpiConfigTxWci: 11
QpiCrcMode: 0
QpiCpuSktHotPlugEn: 0
QpiCpuSktHotPlugTopology: 0
QpiSkuMismatchCheck: 1
QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6
QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11
Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0
******* Common Setup Structure *******
mmCfgBase: 0x80000000
mmCfgSize: 0x10000000
mmiolBase: 0x90000000
mmiolSize: 0x6C000000
mmiohBase: 0x00003800-00000000
mmiohSize: 256 GB
numaEn: 1
isocEn: 0
mesegEn: 0
dcaEn: 1
******* Common Var Structure *******
resetRequired: 0
state: 0
numCpus: 0
socketPresentBitMap: 0x01
busIio: 0x00 0x00 0x00 0x00
busUncore: 0xFF 0x00 0x00 0x00
mmCfgBase: 0x80000000
;******* Collecting Early System Information - START *******
CAPID0[5] is set. SKU Detected as DE.
SocketId: 0 Physical Chop: 3
SocketId: 0 CAPID5: 0x06000B6D
SocketId: 0 CAPID4: 0x24080F02
SocketId: 0 CAPID3: 0x009B0220
SocketId: 0 CAPID2: 0x53B40000
SocketId: 0 CAPID1: 0x8C000083
SocketId: 0 CAPID0: 0x00108120
; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x01 CAPID4[sbsp]:
0x24080F02
; Total Cbos: 08 Cbo List: 0xB6D Total HA: 01 Total R3Qpi: 00 Total
QpiAgent: 00
; TotCpus: 1 CpuList: 0x01
; busIio: 0x00
; busUncore: 0xFF
; Reset Type: Warm Reset Link Speed: Slow Speed
;******* Collecting Early System Information - END *******
;******* Setting up Minimum Path - START *******
; Constructing SBSP minimum path Topology Tree
; --------------------------------------------
; Adding SBSP (CPU0) to the tree
CPU0 Link Exchange
UseQpiPcSts = 1
;SBSP Minimum Path Tree
;----------------------
;Index Socket ParentPort Hop ParentIndex
; 00 CPU0 -- 0 --
;******* Setting up Minimum Path - END *******
;******* Initialize MCTP - START *******
;******* Initialize MCTP - END *******
;******* Check for QPI Topology Degradation - START *******
;Link Exchange Parameter
;-----------------------
;CPU0
; Already Reduced to Supported Topology
; System will be treated 1S Configuration
;******* Check for QPI Topology Degradation - END *******
;******* Checking QPIRC Input Structure - START *******
; Sys configuration Type = 16
;******* Checking QPIRC Input Structure - END *******
;******* Allocate RTIDs - START *******
; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 15 Extra - 06
; Local Base - 01 Reallocation Base - 65
; Cbo 04 RTID straddles into xRTID space
; RTIDs split into three pools of size 3, 8 and 4
; Sufficient extra RTIDs are available to move all the RTIDs into xRTID
space. No loss of RTIDs for the CBo.
; RTID Allocation Table
; ---------------------
; Local
; -----
; WB 0 1
; UBOX 0 0
; ISOC 1 0
; CBO00 1 8
; CBO00 9 7
; CBO01 16 8
; CBO01 24 7
; CBO02 31 8
; CBO02 39 7
; CBO03 46 8
; CBO03 54 7
; CBO04 65 8
; CBO04 73 7
; CBO05 80 8
; CBO05 88 7
; CBO06 95 8
; CBO06 103 7
; CBO07 110 8
; CBO07 118 7
; EXTRA 0 3
;******* Allocate RTIDs - END *******
;******* Cacluate Resource Allocation - START *******
;CPU Resource Allocation
;-----------------------
;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF
MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF
;******* Cacluate Resource Allocation - END *******
;******* Check for QPI Topology change across reset - START *******
;******* Check for QPI Topology change across reset - END *******
;******* Phy/Link Updates On Warm Reset - START *******
; Force unused links to disabled/low power state.
; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF
Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF
; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF
Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF
;******* Phy/Link Updates On Warm Reset - END *******
;******* Sync Up PBSPs - START *******
; Verifying if the remote socket(s) checked-in.
;******* Sync Up PBSPs - END *******
; Wait for mailbox ready
; Send Data portion of command. Socket = 0 Data sent == 0x0
; Send Pcode mailbox command. Socket = 0 Command sent == 0x91
; Wait for mailbox ready
;******* Topology Dicovery and Optimum Route Calculation - START *******
; Locating the Rings Present in the Topology
; No Rings Found
; Constructing Topology Tree
; Adjacency Table
; ----------------
; Checking for Deadlock...
;CPU0 Topology Tree
;-------------------
;Index Socket ParentSocket ParentPort ParentIndex Hop
; 00 CPU0 -- -- -- 0
;
; Calculating Route for CPU0
;CPU 0 Routing Table
;-------------------
;DestSocket Port
;******* Topology Dicovery and Optimum Route Calculation - END *******
;******* Program Optimum Route Table Settings - START *******
;******* Program Optimum Route Table Settings - END *******
;******* Program Final IO SAD Setting - START *******
;******* Program Final IO SAD Setting - END *******
;******* Program Misc. QPI Parameters - START *******
Lock QPI DFX.
;******* Program Misc. QPI Parameters - END *******
;******* Program Home Agent Credits - START *******
; Override credits for CBO with HCC DHT case
;******* Program Home Agent Credits - END *******
;******* Program Home tracker and Route Back Table - START *******
;******* Program Home tracker and Route Back Table - END *******
;******* Program System Coherency Registers - START *******
;******* Program System Coherency Registers - END *******
;******* Check for S3 Resume - START *******
;******* Check for S3 Resume - END *******
;******* Collect Previous Boot Error - START *******
;******* Collect Previous Boot Error - END *******
******* QPI Output Structure *******
OutLegacyVgaSoc: 0
OutIsocEn: 0
OutMesegEn: 0
OutIsocAzaliaVc1En: 0
OutClusterOnDieEn: 0
OutIBPECIEn: 1
OutE2EParityEn: 0
OutEarlySnoopEn: 1
OutHomeDirWOSBEn: 0
QpiCurrentLinkSpeedMode: 0 (SLOW)
OutQpiLinkSpeed: 6
OutQpiLinkL0pEn: 1
OutQpiLinkL1En: 1
OutQpiLinkL0rEn: 1
OutIioUniphyDisable: 0, 0, 0, 0
OutQpiCrcMode: 0
OutClusterOnDieReduction: 0
OutPointerSeperationHA: 0
QpiInternalGlobal->BtModeEn: 0
QpiInternalGlobal->BtMode: 0
QpiInternalGlobal->BtMode2Alt: 0
QpiInternalGlobal->Sys4SClusterOnDieEn: 0
QpiInternalGlobal->SnoopFanoutEn: 0
QpiInternalGlobal->SysSnoopMode: 0
QpiInternalGlobal->IodcEn: 0
;******* QPIRC Exit *******
QPI Init completed! Reset Requested: 0
Pipe Init starting...Pipe Init completed! Reset Requested: 0
CPU Feature Early Config starting...
CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset
Requested: 0
PrevBootErrors - CBO mcbank: 18 - not present; skipping...
PrevBootErrors - CBO mcbank: 21 - not present; skipping...
PrevBootErrors - Valid MCA UC entries: 0
START_MRC_RUN
ME UMA: ME UMA Size Requested: 0
ME UMA size = 0 MBytes
forceColdBoot bit set
Get socket PPIN
Socket not PPIN Capable
setupChanged: 1
Clearing the MRC NVRAM structure.
bootMode = NormalBoot
subBootMode = ColdBoot
Dispatch Slaves -- Started
Dispatch Slaves - 0ms
Promote Warning Exception List -- Started
Promote Warning Exception List - 3ms
Initialize Throttling Early -- Started
Initialize Throttling Early - 150ms
Detect DIMM Configuration -- Started
Detect DIMM Configuration - 838ms
Get Slave Data -- Started
Get Slave Data - 2ms
Check POR Compatibility -- Started
RDIMM population
Check POR Compatibility - 20ms
Initialize DDR Clocks -- Started
GetPORDDRFreq returns ddrfreq = 10
Memory behind processor 0 running at DDR-2133
Initialize DDR Clocks - 71ms
Send Status -- Started
Send Status - 2ms
Set Vdd -- Started
Set Vdd - 36ms
Check DIMM Ranks -- Started
Check DIMM Ranks - 75ms
Send Data -- Started
Send Data - 2ms
Initialize Memory -- Started
Initialize Memory - 4ms
Gather SPD Data -- Started
Gather SPD Data - 2197ms
Configure XMP -- Started
Configure XMP - 194ms
Platform NVDIMM Status -- Started
N0: CoreNVDIMMStatus
Platform NVDIMM Status - 16ms
Early Configuration -- Started
Early Configuration - 229ms
DDRIO Initialization -- Started
N0.C1: Number of DIMMS in channel: 1
DDRIO Initialization - 131301ms
Pre-Training Initialization -- Started
Pre-Training Initialization - 6ms
Early CTL/CLK -- Started
Early CTL/CLK - 148589ms
Early CMD/CLK -- Started
Early CMD/CLK - 636535ms
Lrdimm BS Phase RX -- Started
Lrdimm BS Phase RX - 0ms
Lrdimm BS Cycle RX -- Started
Lrdimm BS Cycle RX - 0ms
Lrdimm BS Delay RX -- Started
Lrdimm BS Delay RX - 0ms
Receive Enable -- Started
Receive Enable - 35009ms
Rx Dq/Dqs Basic -- Started
Rx Dq/Dqs Basic - 13705ms
Lrdimm BS Fine WL -- Started
Lrdimm BS Fine WL - 0ms
Lrdimm BS Coarse WL -- Started
Lrdimm BS Coarse WL - 0ms
Lrdimm BS Delay TX -- Started
Lrdimm BS Delay TX - 0ms
Write Leveling -- Started
Write Leveling - 37226ms
Write Fly By -- Started
Write Fly By - 35807ms
Tx Dq Basic -- Started
Tx Dq Basic - 45511ms
PPR Flow -- Started
PPR Flow - 0ms
Wr Early Vref Centering -- Started
Wr Early Vref Centering - 50341ms
Rd Early Vref Centering -- Started
Rd Early Vref Centering - 60499ms
CMD Vref Centering -- Started
CMD Vref Centering - 29790ms
Late Cmd/Clk -- Started
Late Cmd/Clk - 74595ms
Tx Eq -- Started
Tx Eq - 715899ms
Imode -- Started
Imode - 29ms
CTLE -- Started
CTLE - 648072ms
Tx Per Bit Deskew -- Started
Tx Per Bit Deskew - 0ms
Rx Per Bit Deskew -- Started
Rx Per Bit Deskew - 1ms
Wr Vref Centering (LRDIMM) -- Started
Wr Vref Centering (LRDIMM) - 0ms
Rd Vref Centering (LRDIMM) -- Started
Rd Vref Centering (LRDIMM) - 0ms
Wr Dq Centering (LRDIMM) -- Started
Wr Dq Centering (LRDIMM) - 0ms
Rd Dq Centering (LRDIMM) -- Started
Rd Dq Centering (LRDIMM) - 0ms
Wr Vref Centering -- Started
Wr Vref Centering - 154601ms
Rd Vref Centering -- Started
Rd Vref Centering - 166472ms
Tx Dq Adv -- Started
Tx Dq Adv - 707233ms
Rx Dq/Dqs Adv -- Started
Rx Dq/Dqs Adv - 278320ms
Round Trip Optimization -- Started
Round Trip Optimization - 0ms
Display Training Results -- Started
Display Training Results - 2286ms
Post-Training Initialization -- Started
Post-Training Initialization - 911ms
Rank Margin Tool -- Started
Rank Margin Tool - 0ms
Fill BDAT Structure -- Started
Fill BDAT Structure - 0ms
Platform Restore NVDIMMs -- Started
Platform Restore NVDIMMs - 2ms
Platform Arm NVDIMMs -- Started
Platform Arm NVDIMMs - 1ms
Late Configuration -- Started
Late Configuration - 248ms
Initialize Throttling -- Started
Initialize Throttling - 513ms
Advanced MemTest -- Started
Advanced MemTest - 0ms
MemTest -- Started
MemTest - 7571ms
MemInit -- Started
MemInit - 4029ms
Check Ras Support After MemInit -- Started
Check Ras Support After MemInit - 54ms
Switch to Normal Mode -- Started
Switch to Normal Mode - 154ms
Get NVRAM Data -- Started
Get NVRAM Data - 2ms
Initialize Memory Map -- Started
Initialize Memory Map - 268ms
Set RAS Configuration -- Started
Set RAS Config
Set RAS Configuration - 78ms
Memory Late -- Started
Memory Late - 36ms
DIMM Information -- Started
START_DIMMINFO_TABLE
======================================================================================
START_SOCKET_0_TABLE
BDX B0 - DE
======================================================================================
S| Channel 0 | Channel 1 | Channel 2 | Channel 3
|
======================================================================================
0| Not installed | DIMM: Micron | Not installed | Not
installed |
| | DRAM: Micron | |
|
| | RCD: IDT | |
|
| | 32GB(8Gbx4 1H DR) | |
|
| | DDR4 RDIMM R/C-B | |
|
| | 2400 15-15-15 | |
|
| | ww15 2017 | |
|
| |36ASF4G72PZ-2G3B1 | |
|
| |0x0000000000000000 | |
|
| | | |
|
--------------------------------------------------------------------------------------
1| Not installed | Not installed | Not installed | Not
installed |
--------------------------------------------------------------------------------------
STOP_SOCKET_0_TABLE
======================================================================================
======================================================================================
| Socket 0 | Socket 1 | Socket 2 | Socket 3 |
System |
======================================================================================
Active Memory | 32GB | N/A | N/A | N/A |
32GB |
DDR Freq | | | | |
DDR4-2133 |
Ch1 CL-RCD-RP-CMD |15-15-15-1n | | | |
|
DDR Vdd | | | | |
1.20V |
ECC Checking | | | | |
On |
CAP Checking | | | | |
On |
Patrol/Demand Scrub | | | | |
On/On |
RAS Mode | | | | |
Indep |
Xover Mode | | | | |
2:2 |
Paging Policy | | | | | Adapt
Open |
Data Scrambling | | | | |
On |
CCMRC Revision | | | | |
00.50.00 |
RC Revision | | | | |
02.00.00 |
======================================================================================
STOP_DIMMINFO_TABLE
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Platform DIMM Configuration
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Socket : 0
Channel : 0 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0
Channel : 1 ddr4Size : 512 volSize : 0 perSize : 0 blkSize : 0
Channel : 2 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0
Channel : 3 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0
DIMM Information - 3042ms
Total MRC time = 3995886ms
Setting Last Boot Date = 6245 days
STOP_MRC_RUN
nvram[0].ppin.hi: 0x0, var[0].ppin.hi: 0x0
nvram[0].ppin.lo: 0x0, var[0].ppin.lo: 0x0
Install EFI Memory
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
MRC: lowMemBase:0 lowMemSize:20
MRC: highMemBase:40 highMemSize:1E0
TSEG Unaligned Size is 0x00800000
TSEG Aligned Size is 0x00800000
Low Memory Discovered at 0x00000000 - 0x7F800000
PeiInstallPeiMemory MemoryBegin 0x7F000000, MemoryLength 0x800000
TopOfHighMem 0x880000000
High Memory Discovered at 0x100000000 - 0x880000000
Save NVRAM restore data into Hob
MRC status = 00000000
UMA: Memory retrain occurred during warm reset. Force ME FW reload.
ME UMA: ------------- MePlatformPolicyPpi Dump Begin -------------
Revision : 0x2
DidEnabled : 0x1
DidTimeout : 0x0
DidInitStat : 0x0
ME UMA: ------------- MePlatformPolicyPpi Dump End ----------------
ME UMA: Entered ME DRAM Init Done procedure.
ME UMA: MeUmaBase read: FFF80000
ME UMA: InitStat: 3
ME UMA: ME H_GS written: 1300FFFF
ME UMA: HFS read before DID ACK: 0x000F0382
ME UMA: BiosAction = 0
MeDramInitDone Complete. Checking for reset...
ME UMA: MeFwsts2 = 10406006.
ME UMA: DID Ack was not received, no BIOS Action to process.
Reset Requested: 0
Pipe Exit starting...Pipe Exit completed! Reset Requested: 0
Checking for Reset Requests ... None
Continue with system BIOS POST ...
mmCfgBase 80000000
QPI: CPU[0] bus = FF
QPI: IIO[0] bus = 0
QPI: IIO[0] busbase = 0 Limit=FF
QPI: IIO[0] IoBase = 0 IoLimit=FFFF
QPI: IIO[0] IoApicBase = FEC00000 IoApicLimit=FEC3FFFF
QPI: IIO[0] Mem32Base = 90000000 Mem32Limit=FBFFFFFF
QPI: IIO[0] VtdBarAddress = FBFFC000 RcbaAddress=FBFFE000
PCI: IIO[0] NEW!PciResourceMem32Limit=FBFFBFFF
QPI: CPU[1] is invalid
QPI: IoApic[1] is invalid
QPI: CPU[2] is invalid
QPI: IoApic[2] is invalid
QPI: CPU[3] is invalid
QPI: IoApic[3] is invalid
QPI: num of Cpus = 1
QPI: num of IIOs = 1
Node:0 BaseAddress:00000000 ElementSize:00000220
Setting pam0_hienable = 3
Setting pam1_loenable = 3
Setting pam1_hienable = 3
Setting pam2_loenable = 3
Setting pam2_hienable = 3
Setting pam3_loenable = 3
Setting pam3_hienable = 3
Setting pam4_loenable = 3
Setting pam4_hienable = 3
Setting pam5_loenable = 3
Setting pam5_hienable = 3
Setting pam6_loenable = 3
Setting pam6_hienable = 3
PeimMemoryQpiInit END
Temp Stack : BaseAddress=0xFE184000 Length=0x7C000
Temp Heap : BaseAddress=0xFE108000 Length=0x27210
Total temporary memory: 1015808 bytes.
temporary memory stack ever used: 482044 bytes.
temporary memory heap used: 160272 bytes.
Old Stack size 507904, New stack size 1048576
Heap Offset = 0x0 Stack Offset = 0x7F100000
Stack Hob: BaseAddress=0x7F000000 Length=0x100000
Loading PEIM at 0x0007F7F7190 EntryPoint=0x0007F7F814C
Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry
point: FFEFD9DE
Memory Discovered Notify invoked ...
Loading PEIM at 0x0007F7F2188 EntryPoint=0x0007F7F29D0
Install PPI: EE4E5898-3914-4259-9D6E-DC7BD79403CF
Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
Loading PEIM at 0x0007F7E9000 EntryPoint=0x0007F7E96F8
Install PPI: 057A449A-1FDC-4C06-BFC9-F53F6A99BB92
Loading PEIM at 0x0007F7D4000 EntryPoint=0x0007F7D56B0
PowerStateAfterG3 Default has been overridden by UPD option to 0
FspNvsSave() - Start
FspNvsSave() - End
Install PPI: A7CED760-C71C-4E1A-ACB1-89604D5216CB
Install PPI: 15344673-D365-4BE2-8513-1497CC07611D
Loading PEIM at 0x0007F7BF000 EntryPoint=0x0007F7C15E4
InstallPchInitPpi() - Start
Rcba needs to be programmed before here
PchMiscEarlyInit() - Start
PchMiscEarlyInit() - End
Install PPI: ED097352-9041-445A-80B6-B29D509E8845
Install PPI: 09EA894A-BE0D-4230-A003-EDC693B48E95
Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D
Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry
point: 7F7C261D
PchInitialize() - Start
PchSataInit() - Start
PchSataInit() - End
[MPHY] Creating HOB to adjust Hsio settings from DXE, if required.
[MPHY] SystemConfiguration.MeMphyDebugEnableSurvivabilityTable:0
[MPHY] SystemConfiguration.MeMphyDebugCorruptEndpoints:0
[MPHY] Suppress passing the expected ChipsetInit table to the DXE code, and
further on to ME
Unsupported PCH Stepping for PchDmiHsio
PchInitialize() - End
Install PPI: 1EDCBDF9-FFC6-4BD4-94F6-195D1DE17056
InstallPchInitPpi() - End
Loading PEIM at 0x0007F7B4000 EntryPoint=0x0007F7B4C58
DEBUG:::: IioDmiInitPeiEntryPoint()
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry
point: 7F7B4ED0
PchDmiGen2Prog() Start
PchDmiGen2Prog() End
DEBUG:::: DmiVc1 = 0 ; DmiVcp = 0 ; DmiVcm = 0
Register PPI Notify: 1E2ACC41-E26A-483D-AFC7-A056C34E087B
Notify: PPI Guid: 1E2ACC41-E26A-483D-AFC7-A056C34E087B, Peim notify entry
point: 7F7B5781
DEBUG:::: IioSouthComplexPeiInit()
Enable/disable the SC CBDMA and GbE ports in the IIO IOSF
bridge...(0,2,0,0x190) = 0x33
Loading PEIM at 0x0007F7A5000 EntryPoint=0x0007F7A6290
Install PPI: 0067835F-9A50-433A-8CBB-852078197814
Loading PEIM at 0x0007F760000 EntryPoint=0x0007F76DBB4
IsocEn changed because QPI config. IsocEn =0
Bifurcation of the ConfigIOU1 (Port#3) for CBM will be updated to = 0
Bifurcation of the ConfigIOU2 (Port#1) for CBM will be updated to = 1
Install PPI: DDC3080A-2740-4EC2-9AA5-A0ADEFD6FF9C
Socket 0 does not support uplink port!
Update iioErrPinDatReg = 7
Program Uniphy recipe Revision 4.00
Program RX Recipe values Start.
B0 D6 F0 O30760h = 0x55
B0 D6 F1 O31760h = 0xAAAA
B0 D7 F0 O38760h = 0xAAAAAAAA
B0 D6 F0 O30710h = 0x208
B0 D6 F1 O31710h = 0x208208
B0 D7 F0 O38710h = 0x8208208
B0 D7 F0 O38714h = 0x8208
B0 D6 F0 O30708h = 0x410
B0 D6 F1 O31708h = 0x410410
B0 D7 F0 O38708h = 0x10410410
B0 D7 F0 O3870Ch = 0x10410
B0 D6 F0 O30704h = 0x12
B0 D6 F1 O31704h = 0x492
B0 D7 F0 O38704h = 0x492492
B0 D6 F0 O30700h = 0x24
B0 D6 F1 O31700h = 0x924
B0 D7 F0 O38700h = 0x924924
B0 D6 F0 O30730h = 0x0
B0 D6 F1 O31730h = 0x0
B0 D7 F0 O38730h = 0x0
B0 D6 F0 O30734h = 0x0
B0 D6 F1 O31734h = 0x0
B0 D7 F0 O38734h = 0x0
B0 D7 F0 O38738h = 0x0
B0 D6 F0 O30A50h = 0x3
B0 D6 F1 O31A50h = 0xF
B0 D7 F0 O38A50h = 0xFF
B0 D6 F0 O30A60h = 0x0
B0 D6 F1 O31A60h = 0x0
B0 D7 F0 O38A60h = 0x0
B0 D6 F1 O31A64h = 0xAA
B0 D7 F0 O38A64h = 0xAAAA
B0 D6 F0 O30788h = 0xAA
B0 D6 F1 O31788h = 0xAAAA
B0 D7 F0 O38788h = 0xAAAAAAAA
B0 D6 F0 O30780h = 0xA
B0 D6 F1 O31780h = 0xAA
B0 D7 F0 O38780h = 0xAAAA
B0 D6 F0 O30790h = 0xF
B0 D6 F1 O31790h = 0xFF
B0 D7 F0 O38790h = 0xFFFF
B0 D6 F0 O306ECh = 0x42108
B0 D6 F1 O316ECh = 0x10842108
B0 D6 F1 O316F0h = 0x108
B0 D7 F0 O386ECh = 0x10842108
B0 D7 F0 O386F0h = 0x10842108
B0 D7 F0 O386F4h = 0x42108
B0 D6 F1 O316E0h = 0x16B5AD6B
B0 D6 F1 O316E4h = 0x16B
B0 D7 F0 O386E0h = 0x16B5AD6B
B0 D7 F0 O386E4h = 0x16B5AD6B
B0 D7 F0 O386E8h = 0x5AD6B
B0 D6 F0 O307B0h = 0xFF
B0 D6 F1 O317B0h = 0xFFFF
B0 D7 F0 O387B0h = 0xFFFFFFFF
B0 D6 F0 O30798h = 0xF
B0 D6 F1 O31798h = 0xFF
B0 D7 F0 O38798h = 0xFFFF
B0 D6 F0 O30794h = 0x0
B0 D6 F1 O31794h = 0x0
B0 D7 F0 O38794h = 0x0
B0 D6 F0 O307A0h = 0x0
B0 D6 F1 O317A0h = 0x0
B0 D7 F0 O387A0h = 0x0
B0 D7 F0 O387A4h = 0x0
B0 D6 F0 O306C8h = 0x5
B0 D6 F1 O316C8h = 0x55
B0 D7 F0 O386C8h = 0x5555
B0 D6 F0 O306CCh = 0x3
B0 D6 F1 O316CCh = 0xF
B0 D7 F0 O386CCh = 0xFF
B0 D6 F7 O37650h = 0xC
B0 D6 F0 O306ACh = 0xF
B0 D6 F1 O316ACh = 0xFF
B0 D7 F0 O386ACh = 0xFFFF
B0 D6 F0 O306A0h = 0xFF
B0 D6 F1 O316A0h = 0xFFFF
B0 D7 F0 O386A0h = 0xFFFFFFFF
B0 D6 F1 O31A38h = 0x380038
B0 D6 F1 O31A3Ch = 0x380038
B0 D7 F0 O38A38h = 0x380038
B0 D7 F0 O38A3Ch = 0x380038
B0 D7 F0 O38A40h = 0x380038
B0 D7 F0 O38A44h = 0x380038
B0 D6 F1 O31A88h = 0x5555
B0 D7 F0 O38A88h = 0x55555555
B0 D6 F0 O30A8Ch = 0x55
B0 D6 F1 O31A8Ch = 0x5555
B0 D7 F0 O38A8Ch = 0x55555555
B0 D6 F1 O31A90h = 0xBBBB
B0 D7 F0 O38A90h = 0xBBBBBBBB
B0 D6 F0 O30840h = 0x1EF
B0 D6 F1 O31840h = 0x5AD6B
B0 D7 F0 O38840h = 0x16B5AD6B
B0 D7 F0 O38844h = 0x16B
B0 D6 F0 O30838h = 0x16B
B0 D6 F1 O31838h = 0x9CE73
B0 D7 F0 O38838h = 0x2739CE73
B0 D7 F0 O3883Ch = 0x273
B0 D6 F7 O37644h = 0x238100
B0 D6 F7 O37648h = 0x14000200
B0 D6 F7 O37628h = 0x12
B0 D6 F7 O37638h = 0x132
B0 D6 F7 O37614h = 0x202C000
B0 D6 F7 O3760Ch = 0xB
B0 D6 F7 O37608h = 0x5000010
B0 D6 F7 O37608h = 0x5000010
B0 D6 F7 O37608h = 0x5000030
B0 D6 F7 O37634h = 0x24010
B0 D6 F7 O37654h = 0x1
B0 D6 F0 O30300h = 0x81300000
B0 D6 F1 O31300h = 0x81300000
B0 D6 F2 O32300h = 0x81300000
B0 D7 F0 O38300h = 0x81300000
B0 D7 F1 O39300h = 0x81300000
B0 D7 F2 O3A300h = 0x81300000
B0 D7 F3 O3B300h = 0x81300000
B0 D6 F0 O30300h = 0x81300000
B0 D6 F1 O31300h = 0x81300000
B0 D6 F2 O32300h = 0x81300000
B0 D7 F0 O38300h = 0x81300000
B0 D7 F1 O39300h = 0x81300000
B0 D7 F2 O3A300h = 0x81300000
B0 D7 F3 O3B300h = 0x81300000
B0 D6 F0 O30300h = 0x81300000
B0 D6 F1 O31300h = 0x81300000
B0 D6 F2 O32300h = 0x81300000
B0 D7 F0 O38300h = 0x81300000
B0 D7 F1 O39300h = 0x81300000
B0 D7 F2 O3A300h = 0x81300000
B0 D7 F3 O3B300h = 0x81300000
B0 D6 F0 O306B0h = 0x0
B0 D6 F1 O316B0h = 0x0
B0 D7 F0 O386B0h = 0x0
B0 D7 F0 O386B4h = 0x0
B0 D1 F0 O825Ch = 0x2777
B0 D1 F1 O925Ch = 0x2777
B0 D3 F0 O1825Ch = 0x2777
B0 D3 F1 O1925Ch = 0x2777
B0 D3 F2 O1A25Ch = 0x2777
B0 D3 F3 O1B25Ch = 0x2777
B0 D6 F0 O307C0h = 0x36
B0 D6 F1 O317C0h = 0xDB6
B0 D7 F0 O387C0h = 0xDB6DB6
B0 D6 F0 O30480h = 0xAE0449E2
B0 D6 F1 O31480h = 0xAE0449E2
B0 D7 F0 O38480h = 0xAE0449E2
B0 D6 F0 O30464h = 0x70BFE3
B0 D6 F1 O31464h = 0x70BFE3
B0 D7 F0 O38464h = 0x70BFE3
B0 D6 F1 O31464h = 0x73FFE3
B0 D7 F0 O38464h = 0x73FFE3
B0 D6 F0 O30490h = 0x4
B0 D6 F1 O31490h = 0x4
B0 D6 F2 O32490h = 0x4
B0 D7 F0 O38490h = 0x4
B0 D7 F1 O39490h = 0x4
B0 D7 F2 O3A490h = 0x4
B0 D7 F3 O3B490h = 0x4
B0 D6 F0 O304BCh = 0x9439104
B0 D6 F1 O314BCh = 0x9439105
B0 D7 F0 O384BCh = 0x9439105
B0 D6 F0 O30B04h = 0x48087185
B0 D6 F1 O31B04h = 0x48006181
B0 D7 F0 O38B04h = 0x48006181
B0 D6 F0 O303F4h = 0x8A340C10
B0 D6 F1 O313F4h = 0x8A340C10
B0 D7 F0 O383F4h = 0x8A340C10
B0 D6 F0 O3048Ch = 0x2120000
B0 D6 F1 O3148Ch = 0x2020000
B0 D7 F0 O3848Ch = 0x2020000
B0 D6 F0 O304C4h = 0x10083
B0 D6 F1 O314C4h = 0x10083
B0 D7 F0 O384C4h = 0x10083
B0 D6 F1 O3139Ch = 0x641000
B0 D6 F2 O3239Ch = 0x641000
B0 D7 F0 O3839Ch = 0x641000
B0 D7 F1 O3939Ch = 0x641000
B0 D7 F2 O3A39Ch = 0x641000
B0 D7 F3 O3B39Ch = 0x641000
B0 D6 F1 O313F0h = 0x3C002000
B0 D7 F0 O383F0h = 0x3C002000
B0 D6 F1 O313FCh = 0x2
B0 D7 F0 O383FCh = 0x2
B0 D6 F1 O313CCh = 0x1000480
B0 D6 F2 O323CCh = 0x1000480
B0 D7 F0 O383CCh = 0x1000480
B0 D7 F1 O393CCh = 0x1000480
B0 D7 F2 O3A3CCh = 0x1000480
B0 D7 F3 O3B3CCh = 0x1000480
B0 D6 F1 O31438h = 0x2057F
B0 D7 F0 O38438h = 0x2057F
B0 D6 F1 O31B24h = 0x10011
B0 D7 F0 O38B24h = 0x10011
Program RX Recipe values End.
Gen3: Gen3PrelinkOverride(SKT=0, PORT=1a(1), Phase2=0, Phase3=11)
Gen3: Gen3PrelinkOverride(SKT=0, PORT=1b(2), Phase2=0, Phase3=11)
Gen3: Gen3PrelinkOverride(SKT=0, PORT=3a(7), Phase2=0, Phase3=11)
Gen3: Gen3PrelinkOverride(SKT=0, PORT=3b(8), Phase2=0, Phase3=11)
Gen3: Gen3PrelinkOverride(SKT=0, PORT=3c(9), Phase2=0, Phase3=11)
Gen3: Gen3PrelinkOverride(SKT=0, PORT=3d(10), Phase2=0, Phase3=11)
PcieLinkTrainingInit at device scanning...
IIO=0, IOU2=1.
IIO=0, IOU0=3.
IIO=0, IOU1=0.
DumpIioPcieLinkStatus().....
Skt[0], D[1]:F[0] Link Down!
Skt[0], D[1]:F[1] Link Down!
Skt[0], D[2]:F[0] Link up as x01 Gen1!
Skt[0], D[2]:F[1] Link up as x01 Gen1!
Skt[0], D[2]:F[2] Link up as x01 Gen1!
Skt[0], D[2]:F[3] Link up as x01 Gen1!
Skt[0], D[3]:F[0] Link Down!
Skt[0], D[3]:F[1] Link Down!
Skt[0], D[3]:F[2] Link Down!
Skt[0], D[3]:F[3] Link Down!
Gen3: Gen3Override(SKT=0, PORT=1a(1), Phase2=0, Phase3=11)
Socket:[0] Port:[1] GEN3 retrain reset skipped...
Gen3: Gen3Override(SKT=0, PORT=1b(2), Phase2=0, Phase3=11)
Gen3: Gen3Override(SKT=0, PORT=3a(7), Phase2=0, Phase3=11)
Socket:[0] Port:[7] GEN3 retrain reset skipped...
Gen3: Gen3Override(SKT=0, PORT=3b(8), Phase2=0, Phase3=11)
Socket:[0] Port:[8] GEN3 retrain reset skipped...
Gen3: Gen3Override(SKT=0, PORT=3c(9), Phase2=0, Phase3=11)
Socket:[0] Port:[9] GEN3 retrain reset skipped...
Gen3: Gen3Override(SKT=0, PORT=3d(10), Phase2=0, Phase3=11)
Socket:[0] Port:[10] GEN3 retrain reset skipped...
Program WA 4986406
Skt[0], D[1]:F[0] : Link Down , WA not required!
Skt[0], D[3]:F[0] : Link Down , WA not required!
Skt[0], D[3]:F[1] : Link Down , WA not required!
Skt[0], D[3]:F[2] : Link Down , WA not required!
Skt[0], D[3]:F[3] : Link Down , WA not required!
DumpIioPcieLinkStatus().....
Skt[0], D[1]:F[0] Link Down!
Skt[0], D[1]:F[1] Link Down!
Skt[0], D[2]:F[0] Link up as x01 Gen1!
Skt[0], D[2]:F[1] Link up as x01 Gen1!
Skt[0], D[2]:F[2] Link up as x01 Gen1!
Skt[0], D[2]:F[3] Link up as x01 Gen1!
Skt[0], D[3]:F[0] Link Down!
Skt[0], D[3]:F[1] Link Down!
Skt[0], D[3]:F[2] Link Down!
Skt[0], D[3]:F[3] Link Down!
DMI IIOInitPhase1...
Initialize IIO:0 PCIE port:1 Func:0...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:2 Func:0...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:2 Func:2...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:3 Func:0...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:3 Func:1...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:3 Func:2...
PciEarlyInit at device scanning...
Initialize IIO:0 PCIE port:3 Func:3...
PciEarlyInit at device scanning...
DMI IIOInitPhase2...
Enabling PCIE Dev:1 Func:0 Slot Power...
(auto mode) No speed change required!
IIO 0 Port 1 ASPM configured as 0
Vendor specific pcie Link Init port:2 Func0...
Vendor specific pcie Link Init port:2 Func2...
Enabling PCIE Dev:3 Func:0 Slot Power...
(auto mode) No speed change required!
IIO 0 Port 7 ASPM configured as 0
(auto mode) No speed change required!
IIO 0 Port 8 ASPM configured as 0
(auto mode) No speed change required!
IIO 0 Port 9 ASPM configured as 0
(auto mode) No speed change required!
IIO 0 Port 10 ASPM configured as 0
DMI IIOInitPhase3...
DMI Link Retrain()
DMI speed is 5Gb/s (Gen2)
PciPostInit port:1 Func0...
PciPostInit port:2 Func0...
PciPostInit port:2 Func2...
PciPostInit port:3 Func0...
PciPostInit port:3 Func1...
PciPostInit port:3 Func2...
PciPostInit port:3 Func3...
Initialize IIO[0] IOxAPIC...
IIO[0] IOxAPIC Base=FEC01000
IIO[0] TOMMIOL_OB = FEF00000
VT-d Chipset Initialization for IIO0 ...
Vt-D base address : 0x7F1EA405FBFFC000
VtDGenCtrlReg : 0x000080A8
VtDIsoCtrlReg : 0x00000001
Non-Iso Engine CapReg : 0x08D2078C106F0466
Non-Iso Engine ExtCapReg : 0x0000000000F020DF
IIOMISCCTRL for IIO 0 = 0x42030170
Initializing NTB for SKT0
setup PPD 0
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Calling IioClockDisables: Socket=0
IioClockDisables: Socket=0, Port=0
IioClockDisables: Data Link Active or skipped for D0 : F0
IioClockDisables: DisableBitMap=CEE0000
IioClockDisables: Socket=0, Port=1
IioClockDisables: Socket=0, Port=2
IioClockDisables: Socket=0, Port=3
IioClockDisables: Data Link Active or skipped for D2 : F0
IioClockDisables: DisableBitMap=8AA0000
IioClockDisables: Socket=0, Port=4
IioClockDisables: Data Link Active or skipped for D2 : F1
IioClockDisables: DisableBitMap=8AA0000
IioClockDisables: Socket=0, Port=5
IioClockDisables: Data Link Active or skipped for D2 : F2
IioClockDisables: DisableBitMap=8AA0000
IioClockDisables: Socket=0, Port=6
IioClockDisables: Data Link Active or skipped for D2 : F3
IioClockDisables: DisableBitMap=8AA0000
IioClockDisables: Socket=0, Port=7
IioClockDisables: Socket=0, Port=8
IioClockDisables: Socket=0, Port=9
IioClockDisables: Socket=0, Port=10
IIO Port/Clocks Powering down: Socket=0, Disable Bit Map=80220000
IioInit Secure the Platform (TXT)..
IioInit PCIe device hide..
Bus=255, Device=1, Function=1 is hidden.
Bus=255, Device=2, Function=1 is hidden.
Bus=255, Device=2, Function=3 is hidden.
Skt[0], D[1]:F[0] Link Down!
Skt[0], D[2]:F[0] Link up as x01 Gen1!
Skt[0], D[2]:F[2] Link up as x01 Gen1!
Skt[0], D[3]:F[0] Link Down!
Skt[0], D[3]:F[1] Link Down!
Skt[0], D[3]:F[2] Link Down!
Skt[0], D[3]:F[3] Link Down!
Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Loading PEIM at 0x0007F74F000 EntryPoint=0x0007F750310
Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C
Loading PEIM at 0x0007F744000 EntryPoint=0x0007F744ADC
[HECI-0] VID-DID: 8086-8C3A
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Loading PEIM at 0x0007F733000 EntryPoint=0x0007F734814
TempMmioBase = 90000000
TempMmioLimit = FBFFFFFF
TempIoBase = 1000
TempIoLimit = FFFF
XHCI (14h) = 90000000...90003000 (00003000)
EHCI (1Dh) = 90003000...90003400 (00000400)
EHCI2 (1Ah) = 90003400...90003800 (00000400)
SATA (1Fh.2) [AHCI] = 90003800...90004800 (00001000)
PCI Root Port[0] Status from UPD = 1
PCI Root Port[1] Status from UPD = 1
PCI Root Port[2] Status from UPD = 1
PCI Root Port[3] Status from UPD = 1
PCI Root Port[4] Status from UPD = 1
PCI Root Port[5] Status from UPD = 1
PCI Root Port[6] Status from UPD = 1
PCI Root Port[7] Status from UPD = 1
Cpu Type= 0x56, Cpu Stepping= 0x1
Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5
Number of Active Cores / Threads = 8 / 10
:::: CapId5 = 6000B6D, PlatformInfo->CpuData.SkuSlices = B6D
:::: CapId4 = 24080F02, PlatformInfo->CpuData.CpuPCPSInfo = 30010
Socket Present BitMap, mmCfgBase, dimmTypePresent, BoardId, CpuType 1,
80000000, 7F1EA95E, 0 56
EFI_PPM_STRUCT size: 166
:: !!! PPM Revision: Major:00Minor:01Rev:0000!!!.
:: Reading MSR_TURBO_POWER_LIMIT (610) =43815E 0
:: Reading Socket = 0, CSR_TURBO_POWER_LIMIT=0 0
:: Wrote Socket = 0, CSR_PCIE_ILTR_OVRD=0
Program FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE as 100 (39)
Detected Boot Mode 0
Detected 16 CPU threads
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793
Loading PEIM at 0x0007F70A000 EntryPoint=0x0007F70B1CC
PchInitEntryPoint() Start
PCH Device:
-------------
RCBA 0xFED1C000
PmBase 0x400
GpioBase 0x500
-------------
InitializePchDevice() Start
ChipsetInitSettingsCheck() Start
ConfigureMiscPm() Start
ConfigureMiscPm() End
ConfigureDmi() Start
ConfigureDmi() End
ConfigureMiscItems() Start
ConfigureMiscItems() End
ConfigureLan() Start
LAN can be enabled or disabled as SPI is in Descriptor Mode.
ConfigureLan() End
ConfigureUsb() Start
CommonUsbInit() - Start
CommonUsbInit() - End
ConfigureUsb() End
PchInitRootPorts() Start
PCI Root Port[0] Status = 1
PCI Root Port[1] Status = 1
PCI Root Port[2] Status = 1
PCI Root Port[3] Status = 1
PCI Root Port[4] Status = 1
PCI Root Port[5] Status = 1
PCI Root Port[6] Status = 1
PCI Root Port[7] Status = 1
PCI Function 1 disabled as port is not hot plug enabled and no PCIe card is
detected
PCI Function 2 disabled as port is not hot plug enabled and no PCIe card is
detected
PCI Function 3 disabled as port is not hot plug enabled and no PCIe card is
detected
PCI Function 4 disabled as port is not hot plug enabled and no PCIe card is
detected
PCI Function 5 disabled as port is not hot plug enabled and no PCIe card is
detected
PCI Function 6 disabled as specified in the Fuse Straps
PCI Function 7 disabled as specified in the Fuse Straps
PCI Function 8 disabled as specified in the Fuse Straps
PCH PCI Root Port Clock Gating is 1
PchInitRootPorts() End
ConfigureSata() Start
ConfigureSata() End
ConfigureDisplay() Start
ConfigureDisplay() End
PCH PCIe Function Disable Register = 2FF2001.
ConfigureClockGating() Start
ConfigureClockGating() End
ConfigureIoApic() Start
ConfigureIoApic() End
ProgramSvidSid() Start
ProgramSvidSid() End
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
InitializePchDevice() End
PchInitEntryPoint() End
Loading PEIM at 0x0007F6FF000 EntryPoint=0x0007F6FFFBC
[SPS] DXE PHASE
[SPS] Getting Info from PEI
[SPS] Looking for SPS HOB info from PEI
[SPS] HOB: flow 1, feature set 0x0000, pwr opt boot 0, cores2disable 0
[SPS] WARNING: Using PCH temperature from ME is enabled, but ME is not
operational! (MEFS1: 000F0382)
[SPS] SiliconEnabling Mode
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
DXE IPL Entry
FSP HOB is located at 0x7F100000
Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6
FSP is waiting for NOTIFY
U-Boot 2017.09-g842980e-dirty (Jan 02 2018 - 15:16:48 +0100)
CPU: x86_64, vendor Intel, device 50661h
DRAM: 32 GiB
Warning: MP init failure
MMC:
Using default environment
In: serial
Out: serial
Err: serial
Model: Intel Broadwell-DE
Net: No ethernet found.
FSP Got Notification. Notification Value : 0x00000040
Unsupported FSP Notification Value
Hit any key to stop autoboot: 0
** Bad device scsi 0 **
Error: Invalid Boot Flag (found 0x0000, expected 0xaa55)
## Kernel loading failed ...
zboot - Boot bzImage
Usage:
zboot [addr] [size] [initrd addr] [initrd size]
addr - The optional starting address of the bzimage.
If not set it defaults to the environment
variable "fileaddr".
size - The optional size of the bzimage. Defaults to
zero.
initrd addr - The address of the initrd image to use, if any.
initrd size - The size of the initrd image to use, if any.
=>
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