Hello,
I have an at91 based board which starts from NOR flash. I have an ugly
workaround in lowlevel_init.S that switching from slowclock to PLLA is done
from the internal SRAM instead directly from NOR which is not possible as the
NOR flash timing are also affected. So i copied some data
Dear Alexander Stein,
In message 201006161018.48802.alexander.st...@systec-electronic.com you wrote:
A new approach would be to link lowlevel_init directly at 0x0020 (which
is
AT91SAM9260_SRAM0_BASE) but the code is located next to the normal .text
segment. I've prepared a change to
Dear Wolfgang,
Am Mittwoch, 16. Juni 2010 14:56:31 schrieb Wolfgang Denk:
A new approach would be to link lowlevel_init directly at 0x0020
(which is AT91SAM9260_SRAM0_BASE) but the code is located next to the
normal .text segment. I've prepared a change to
cpu/arm926ejs/u-boot.lds (I
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