Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?

Hi Dirk, Thanks i got some useful information. Warm Regards, Akshay --- On Thu, 10/9/09, Dirk Behme dirk.be...@googlemail.com wrote: From: Dirk Behme dirk.be...@googlemail.com Subject: Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache? To: akshay ts taksh

Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?

akshay ts wrote: Hi, I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache. Flush or invalidate? See below... What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be

[U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?

Hi, I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache. What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be present in the cache. Flushing is only required during